Recently, system-on-chip (SoC) solutions have been realized by integrating not only complex digital processing but also extensive analog and radio frequency (RF) circuits in a single chip. This paper presents a novel RF self test methodology suitable for complex radio SoC's. The proposed methodology employs the digital processor embedded in an SoC to enable self-testing using low-cost digital automatic test equipments (ATE). Moreover, to achieve increased RF test coverage achievable through internal loopback, the embedded processor also utilizes a compact assisted test board and interfaces to it through simple general purpose I/O's (GPIO). The proposed self-test methodology has been successfully applied in the mass production (MP) of a 65nm CMOS combo SoC that includes Wi-Fi, Bluetooth, GPS and FM. The final test (FT) and wafer probe test (PT) of the SoC have been accomplished with a 3X reduction in total test time compared to conventional test methodology using RF instruments.

A low-complexity blind frequency-dependent I/Q imbalance compensation scheme is proposed based on linear prediction (LP) method. It provides non-iterative processing which reduces computational complexity. No special training sequence is used and I/Q mismatch calibration is performed using any received sequence. Frequency-dependent (FD) I/Q imbalance can be compensated simply by matching the filter responses of the I and Q branches. This is achieved by estimating the inverse impulse responses of the I and Q branches using LP and then finding the `difference' filter that can be used in one of the branches to match the other branch. Using simulations, we show that the proposed method has at least 5-7 dB better image rejection ratio (IRR) performance compared to other blind FD I/Q estimation techniques in the literature, for a realistic mismatch scenarios. Moreover, the computational complexity of the proposed technique is shown to be 20x less than the least complex blind estimation scheme in the literature for an 8-tap compensation filter. Finally, we propose the use of a noise-generator for offline-calibration.

With the proliferation of multi-standard mobile devices, in-device coexistence (IDC) has become a key challenge in the design of modern radios. Typical IDC use cases involve radio transmitters (aggressors) that are interfering with radio receivers (victims) collocated on the same device. Isolation of the sensitive receiver from high power transmitters on the same device poses major difficulties due to insufficient frequency separation between the aggressors and their victims. In this paper, we present an adaptive approach to suppress unwanted out-of-band signal power (i.e. TX skirt)from the aggressor to minimize desensitization at the victim. The proposed method relaxes off-chip filtering requirements and reduces guard band spacing, leading to a low cost integrated solution for multi-standard radios. To highlight the effectiveness of the proposed algorithm, we have demonstrated greater than 30 dB improvement in signal-to-interference ratio (SIR) enabling the coexistence between Band-40 LTE and 2.4GHz Wi-Fi radios on the same device.

Modern radios use in-phase (I) and quadrature-phase (Q) channels for transmission and reception. However, IQ matching for high image rejection ratio is difficult and costly to realize by pure analog circuit techniques. Therefore, digital-assisted IQ compensation is required. This paper presents a novel joint TX/RX IQ compensation (JTRC) algorithm for low-IF feedback architecture. Conventional approaches are based on time-domain processing of test tones or frequency-domain processing of pilots in orthogonal frequency-division multiplexing (OFDM) systems. In contrast, JTRC employs time-domain blind source separation (BSS) for both OFDM and non-OFDM based systems without placing a specific requirement on the type of test signal. For example, JTRC supports both tones and modulated signals. Moreover, JTRC can be performed in the background during normal transmission mode using the actual transmitted signal. Unlike other BSS approaches that can only compensate for RX IQ mismatches while assuming a matched transmitter, JTRC can jointly compensate for both TX and RX IQ mismatches. We present an in-depth analysis that validates the JTRC algorithm and show simulation results that demonstrate its effectiveness.

Emerging CMOS and MEMS technologies enable the implementation of a large number of wireless distributed microsensors that can be easily and rapidly deployed to form highly redundant, self-configuring, and ad hoc sensor networks. To facilitate ease of deployment, these sensors should operate on battery for extended periods of time. A particular challenge in maintaining extended battery lifetime lies in achieving communications with low power. This paper presents a direct-sequence spread-spectrum modem architecture that provides robust communications for wireless sensor networks while dissipating very low power. The modem architecture has been verified in an FPGA implementation that dissipates only 33 mW for both transmission and reception. The implementation can be easily mapped to an ASIC technology, with an estimated power performance of less than 1 mW.

This paper presents a robust adaptive type-I hybrid ARQ scheme that can adapt to a slowly-varying wireless channel. The proposed system can improve system throughput substantially compared to a conventional type-I hybrid ARQ scheme. Most previous research on adaptive ARQ has assumed that the return channel used for acknowledgements is error free. This simplifying assumption is often necessary for initial performance evaluation but is unrealistic in practice. In this paper, we extend an existing adaptive ARQ scheme by making it robust to channel errors in both the forward and feedback channels. We also propose a solution to maintain code synchronization in the presence of packet errors and describe an implementation that combines the adaptive ARQ scheme with a SACK protocol that allows bi-directional transmission and piggybacked acknowledgements. In addition we have built a wireless test platform for mobile radio in an attempt to accurately measure the adaptive error control performance not only as a standalone entity, but also as a part of a complete protocol stack.

Conventional estimation algorithms utilize either a tone or squarewave in the preamble for frequency estimation. However, such patterns for the preamble sequence are nonoptimal when the channel is frequency-selective. Furthermore, the problem is exacerbated for packet-switched systems which require frequency synchronization on a per-packet basis. This paper presents a low-complexity frequency estimation algorithm that is robust in frequency selective fading channels. The algorithm is non-decision aided and does not require a priori frame synchronization. Compared against conventional techniques, a factor of 5-10 reduction in BER and a factor of 3 reduction in convergence time are achieved.

Spread spectrum systems are being widely deployed today and are becoming more prevalent as most next-generation wireless systems are adopting it for their common air interface. These systems include the digital cellular IS-95A/B/C, IEEE 802.11 wireless local area networks, as well as third-generation wideband code-division multiple access systems. In spread-spectrum systems, the receiver must synchronize on to the transmitted pseudo-noise (PN) code to obtain the improvement performance achieved through spreading. Since PN acquisition must process the spread-spectrum signal at a speed much faster than the transmitted data rate, its energy consumption can become significant and should be minimized for portable applications. Typically, either matched filters or serial correlators are used to acquire the PN code timing. This paper describes a hybrid PN acquisition architecture which employs both matched filters and serial correlators to achieve a lower energy consumption and fast acquisition time as compared to the traditional approaches of using either matched filters or serial correlators alone. The hybrid architecture has been implemented in RTL VHDL and synthesized down to gate level in 0.5-micron CMOS library. Synthesis results show a factor of four reduction in energy for the hybrid scheme as compared to the matched filters architecture and a factor of two reduction in energy as compared to the serial architecture.

The quality of wireless links suffers from time-varying channel degradations such as interference, flat-fading, and frequency-selective fading. Current radios are limited in their ability to adapt to these channel variations because they are designed with fixed values for most system parameters such as frame length, error control, and processing gain. The values for these parameters are usually a compromise between the requirements for worst-case channel conditions and the need for low implementation cost. Therefore, in benign channel conditions these commercial radios can consume more battery energy than needed to maintain a desired link quality, while in a severely degraded channel they can consume energy without providing any quality-of-service (QoS). While techniques for adapting radio parameters to channel variations have been studied to improve link performance, in this paper they are applied to minimize battery energy. Specifically, an adaptive radio is being designed that adapts the frame length, error control, processing gain, and equalization to different channel conditions, while minimizing battery energy consumption. Experimental measurements and simulation results are presented to illustrate the adaptive radio's energy savings.

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel.>