The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in an (n/spl times/n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds.>

The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input maintains a separate queue for each of the outputs, thus there are n/sup 2/ input queues in a (n*n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. The choice of the packets is done in a manner to maximize the throughput of the switch. Comparison of simulations with analytically derived upper and lower bounds show close to optimal throughput. The mean packet delay is also derived and its variance is bounded. This input access scheme may be implemented using neural networks.>