Demo Data from VLDB 2026 / reviewers in the wild / expert
Ashish Dixit
dblp:34/4217
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2001 | Panel: Your Core - My Problem? Integration and Verification of IP · DAC 2001 |
Electronic design automation › design management
design reuse |
0.0 | 1 | 2001 | Panel: Your Core - My Problem? Integration and Verification of IP · DAC 2001 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Panel: Your Core - My Problem? Integration and Verification of IPabstractAs the popularity of reusing existing designs--or Intellectual Property (IP)--continues to grow, design challenges escalate. The most time-consuming and critical part of IP design and reuse is verifying that it will work as it was designed to and as the user intends. Designers are pushing the limits of IP for new, distinctive and innovative applications. With this innovation come problems that need creative solutions. Product verification, for example, will become more and more important in ensuring the correctness of the design. Over the years, various solutions have come on the market, all seemingly useful, but none reducing the time or manpower it takes to verify the design. With designs becoming increasingly more complex with each new project and verification consuming up to 70 percent of a design cycle, something must be done to alleviate the bottleneck. Gabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Janick Bergeron, Ashish Dixit, Peter Flake |
DAC | 8 |