In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is presented. With little addition in computational cost from the traditional event driven simulation the new technique employs better delay modeling of glitch peaks through the introduction of glitch coefficients and appropriate glitch filtering to achieve improvement in accuracy. The simulator is shown to reduce the estimation error by up to 50% from the traditional toggle-based technique, and has accuracy within 10% of SPICE. The simulator post-processes Verilog-XL output and the overall run-time is better than SPICE by more than an order of magnitude.

In this correspondence, the problem of obtaining efficient hardware for Viterbi decoders for high-rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the add-compare-select units required may be classified in terms of structures of which there are only a small number for a given code constraint length. They correspond to the assignment of individual register lengths in the ensemble of shift registers in the feedforward encoder. The structures relate to the partitioning of the states such that common successors are grouped together and successive partitioning leads to a hierarchical, modular VLSI layout method. Example symbolic grid layouts are given for 16- and 64-state codes. It is noted that within a given structure, the parity check matrices map into local wiring patterns implying a method for implementing class-universal programmable or adaptive decoders.

There has recently been some interest in the emerging technique of Sigma Delta Signal Processing (SDSP) where direct processing of the bitstream is proposed as an alternative to the decimation-PCM processing-interpolation cycle required for DSP of /spl Sigma//spl Delta/ converted signals. SDSP requires digital (re)modulation with a variety of wordlengths in the oversampled datastream; the prediction and control of the remodulator complexity is crucial in determining the relative value of SDSP in any given context. This paper addresses this issue in deriving a new method for reducing remodulator complexity and in obtaining its dependence on the datastream wordlength.

This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed.>

Wave Digital Filters are known to be superior in many respects to other IIR filter structures and are suitable for high speed filtering applications. In this paper the two-port adaptor is used to implement both the Lattice and Bireciprocal Wave Digital Filters. The main computational element of the twoport adaptor and all other digital domain filters is the multiplier. Carry save techniques can efficiently implement the shift-and-add multiplication algorithm. Selection of which of the filter coefficient and data operands is the actual multiplier leads to the development of two arrays with different data flow characteristics. This paper compares and contrasts these two carry save arithmetic methodologies and applies them to the Bireciprocal and Lattice Wave Digital Filters. Emphasis will be placed on the usage of efficient pipelining schemes.>