In the past, Virtual-Grid Compactors have not been well received because they generated sparse layouts. In analyzing this problem, we found three major areas where improvements could be made: breaking the virtual-grid lines into segments; decoupling the placement of non-interacting layers; and eliminating the centered nature of elements. The result is a compactor with substantially better mask generation.

This paper describes the VIVID (Vertically Integrated VLSI Design) System developed at the Microelectronics Center of North Carolina. The system is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom VLSI circuits. This methodology has made it possible to provide, in a single integrated system, several unique features: technology independent tools for a wide range of MOS processes (CMOS, nMOS, SOI); scale independent circuit designs; open architecture that simplifies both integration with existing tools and creation of new tools; fast layout debugging using symbolic level circuit simulation; and fully automated mask generation and automated chip assembly.