A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost.It covers a range of 35K to a million usable gates.In addition, it delivers high performance and it is synthesis efficient.This architecture is loosely based on an earlier reprogrammable Actel architecture named ES.By changing the structure of the interconnect and by making other improvements, we achieved an average cost reduction by a factor of three per usable gate.The first member of the family based on this architecture is fabricated on a 2.54 standard 0.25~ CMOS technology with a gate count of up to 130K which also includes 36K bits of two port RAM.The gate count of this part is verified in a fully automatic design flow starting from a high level description followed by synthesis, technology mapping, place and route, and timing extraction.

This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters. A routing model and hierarchical decomposition schemes are presented to address the routability issue. More specifically, this paper focuses on the formulation and analysis of global routing and vertical assignment problems and gives a systematic breakdown of the routing task into well-defined subtasks. Instead of performing sequential routing, techniques and formulations are introduced to achieve a high degree of order independency in all subtasks. In routing subtasks where iterations are required, independent selection and interconnection are performed to avoid order dependency in typical routing problems. Implementation results are provided to indicate the efficiency of the system.

The main thrust of the above paper1appears to be a detailed restatement of the "left-edge algorithm" [1], [2] for channel routing. This algorithm is almost a decade old and is now quite familiar to most workers in the field of LSI design automation. That the authors did not reference this earlier work, and devoted much of their paper to a reexposition certainly detracts from its usefulness.