Modern FPGAs support dual-output LUT to reduce the area of FPGA designs. Several existing works explored the use of dual-output LUTs in approximate computing. However, they are limited to small-scale arithmetic circuits. To address this issue, we propose QUADOL, a quality-driven approximate logic synthesis (ALS) method leveraging dual-output LUTs for modern FPGAs. It can approximately merge two single-output LUTs into a dual-output LUT. The selection of LUTs for approximate merging is formulated as a maximum matching problem to maximize area savings. To further enhance existing ALS methods, we also propose QUADOL+, a generic framework to integrate QUADOL into existing ALS methods. Experimental results showed that QUADOL+ achieves significant area reduction over prior works.

Approximate computing is an emerging paradigm to improve the energy efficiency for error-tolerant applications. Many iterative approximate logic synthesis (ALS) methods were proposed to automatically design approximate circuits. However, as the sizes of circuits grow, the runtime of ALS grows rapidly. Thus, a crucial challenge is to ensure circuit quality while improving the efficiency of ALS. This work proposes a dual-phase iterative framework to accelerate the iterative ALS flows. In the first phase, a comprehensive circuit analysis is performed to gather the necessary information, including the error information. In the second phase, minimal incremental computation is employed based on the information from the first phase. The experimental results show that the proposed method achieves an acceleration by up to 21.8 × without loss of circuit quality compared to the state-of-the-art methods.

Approximate computing emerges as an energy-efficient computing paradigm designed for applications that can tolerate errors. Many iterative methods for approximate logic synthesis (ALS) have been developed to automatically synthesize approximate circuits. Nonetheless, most of them overlook the potential of applying multiple local approximate changes (LACs) simultaneously in one iteration, which can significantly reduce the overall computation time. In this article, we propose AccALS 2.0, a novel framework for further accelerating iterative ALS flows, which is based on simultaneous selection of multiple LACs in a single round. However, there are two challenges for selecting multiple LACs. The first is that the mutual influence of multiple LACs can affect the estimation of the circuit error. The second is that there may exist conflicts among multiple LACs. To address these issues, first, we propose an efficient measure for the mutual influence between two LACs. With its help, we transform the problems of solving the LAC conflicts and selecting multiple LACs into a unified maximum independent set problem for solving. The experimental results showed that AccALS 2.0 outperforms state-of-the-art ALS methods in runtime, while achieving similar or better-circuit quality.

Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers, as a basic component of many processors and accelerators, have been constantly proposed and studied for decades, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high-level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.

Approximate computing is an energy-efficient computing paradigm for error-tolerant applications. To automatically synthesize approximate circuits, many iterative approximate logic synthesis (ALS) methods have been proposed. However, most of them do not consider applying multiple local approximate changes (LACs) in a single round, which can lead to a much shorter runtime. In this paper, we propose AccALS, a novel framework for Accelerating iterative ALS flows, based on simultaneous selection of multiple LACs in a single round. When selecting multiple LACs, there may exist conflicts among them. One important component of AccALS is a novel method to solve the conflicts. Another is an efficient measure for the mutual influence between two LACs. With its help, the problem of selecting multiple LACs is transformed into a maximum independent set problem to solve. The experimental results showed that compared to a state-of-the-art method, AccALS accelerates by up to 24.6× with a negligible circuit quality loss.

Approximate computing is a promising computing paradigm for designing energy-efficient systems. To automatically generate approximate circuits, many local iterative approximate logic synthesis (ALS) methods have been proposed. They need to specify a particular local approximation change and apply it to modify the local structure of a circuit in each round. This will lose some global optimization opportunities, thus, degrading circuit quality. In this paper, we propose DASALS, a differentiable archltecture search-driven ALS method, to directly search the whole circuit structure to obtain the approximate circuits with better circuit quality-accuracy trade-off. DASALS is based on a proper continuous relaxation of the discrete search space of ALS and an efficient gradient descent-based search algorithm. The experimental results show that compared with a state-of-the-art method, DASALS on average reduces the area-delay product by 10.82% and mean square error by 10.93%.

Approximate computing is an emerging computing paradigm to design energy-efficient systems. Many greedy approximate logic synthesis (ALS) methods have been proposed to automatically synthesize approximate circuits. They typically need to consider all local approximate changes (LACs) in each iteration of the ALS flow to select the best one, which is time-consuming. In this paper, we propose SEALS, a Sensitivity-driven Efficient ALS method to speed up a greedy ALS flow. SEALS centers around a newly proposed concept called sensitivity, which enables a fast and accurate error estimation method and an efficient method to filter out unpromising LACs. SEALS can handle any statistical error metric. The experimental results show that it outperforms a state-of-the-art ALS method in runtime by 12X to 15X without reducing circuit quality.

Approximate multiplier is a fundamental arithmetic block for designing energy-efficient systems, which can be realized by approximate 4-2 compressors. However, the prior works all design approximate 4-2 compressors manually, so the area optimality of the circuits cannot be guaranteed. In this paper, given any input distribution and error bound, we propose MinAC, an exact synthesis-based method to automatically produce minimal-area approximate 4-2 compressors. To directly obtain an area-optimal circuit using an industrial gate library, gates with multiple outputs are taken into account during the exact synthesis. The experimental results show that compared with the existing methods, MinAC on average can produce approximate 4-2 compressors with 39.8%, 44.2%, and 7.9% reduction in area-delay-product, power-delay-product, and mean error distance, respectively. The code of MinAC is available at https://github.conySJTU-ECTL/MinAC.

Stochastic computing (SC) operates on stochastic bit streams, which can realize complex arithmetic functions with simple circuits. A previous work shows that by introducing a little approximation error for the target function, the cost of SC circuits can be dramatically reduced. However, the previous heuristic method only explores a limited subset of the solution space, so the optimality of the results cannot be guaranteed. In this paper, we propose MinSC, an exact synthesis-based method for minimal-area stochastic circuits under relaxed error bound. First, a novel search method is proposed to find the best approximation polynomial for a target function. Then, considering gates with different fanin numbers and areas, an exact SC synthesis method using satisfiability modulo theories is designed to obtain an area-optimal SC circuit realizing the best approximation polynomial. The experimental results show that compared with the state-of-the-art method, given an error ratio 0.05, MinSC on average reduces the gate number, area, delay, and area-delay-product of the SC circuits by 60.24%, 47.24%, 7.10%, 57.07%, respectively.