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Zusong Li

dblp:34/4803 · DBLP profile ↗
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4ranked-venue papers
2as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 60% Processor architecture and microarchitecture · 40%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
functional verification
0.612022
Towards Developing High Performance RISC-V Processors Using Agile Methodology · MICRO 2022
Electronic design automation › hardware verification and test
hardware verification
0.612022
Towards Developing High Performance RISC-V Processors Using Agile Methodology · MICRO 2022
Processor architecture and microarchitecture › microprocessor design
RISC-V processor
0.612022
Towards Developing High Performance RISC-V Processors Using Agile Methodology · MICRO 2022
Processor architecture and microarchitecture › superscalar processor
superscalar out-of-order processor
0.612022
Towards Developing High Performance RISC-V Processors Using Agile Methodology · MICRO 2022

Methods — techniques the papers use, named apart from their topics

pre-silicon validation · 0.6performance modeling · 0.6agile methodology · 0.6
YearPublicationVenuePosition
2022 Towards Developing High Performance RISC-V Processors Using Agile Methodology
abstract
While research has shown that the agile chip design methodology is promising to sustain the scaling of computing performance in a more efficient way, it is still of limited usage in actual applications due to two major obstacles: 1) Lack of tool-chain and developing framework supporting agile chip design, especially for large-scale modern processors. 2) The conventional verification methods are less agile and become a major bottleneck of the entire process. To tackle both issues, we propose MINJIE, an open-source platform supporting agile processor development flow. MINJIE integrates a broad set of tools for logic design, functional verification, performance modelling, pre-silicon validation and debugging for better development efficiency of state-of-the-art processor designs. We demonstrate the usage and effectiveness of MINJIE by building two generations of an open-source superscalar out-of-order RISC-V processor code-named XIANGSHAN using agile methodologies. We quantify the performance of XIANGSHAN using SPEC CPU2006 benchmarks and demonstrate that XIANGSHAN achieves industry-competitive performance.
Yinan Xu 0001, Dan Tang 0002, Guokai Chen, Lingrui Gou, Qianruo Li, Zuojun Li, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang 0001, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai 0001, Dandan Huan, Zusong Li, Jiye Zhao, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao
MICRO28
2008 Chip Multithreaded Consistency Model
Zusong Li, Dandan Huan, Weiwu Hu
J. Comput. Sci. Technol.1
2006 Microarchitecture and Performance Analysis of Godson-2 SMT Processor
abstract
This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-of-order execution high performance processor. The condition for implementing correct memory consistency model in Godson-2 SMT processor is studied and a new register-level sharing and synchronization scheme is proposed. Godson-2 SMT processor has been implemented at the RTL level and simulated with the VstationPro of Mentor Graphics. The Linux operating system is ported to run in Godson-2 SMT processor and application programs such as SPEC CPU2000 benchmark suite are used to evaluate performance. Experimental results indicate that the performance of Godson-2 SMT processor is improved significantly by fully exploiting thread-level parallelism and optimized utilization of functional units. The average speedup is 31.3% with 18.8% area overhead.
Zusong Li, Xianchao Xu, Weiwu Hu
ICCD1
2005 Microarchitecture of the Godson-2 Processor
Weiwu Hu, Fuxin Zhang, Zusong Li
J. Comput. Sci. Technol.3