Abstract Formal methods are becoming an indispensable part of the design process in software and hardware industry. It takes robust tools and proofs to make formal validation of large scale projects reliable. In this paper, we will describe the current status of formal verification at Centaur Technology. We will explain our challenges and our methodology—how various proofs and verification artifacts are interconnected and how we keep them consistent over the duration of a project. We also describe our main engine—a powerful symbolic simulator with rewriting capabilities that is integrated in a theorem prover and proven correct.

The automatic formal verification of multiplier designs has been pursued since the introduction of BDDs. We present a new rewriter-based method for efficient and automatic verification of signed and unsigned integer multiplier designs. We have proved the soundness of this method using the ACL2 theorem prover, and we can verify integer multiplier designs with various architectures automatically, including Wallace, Dadda, and 4-to-2 compressor trees, designed with Booth encoding and various types of final stage adders. Our experiments have shown that our approach scales well in terms of time and memory. With our method, we can confirm the correctness of $$1024\times 1024$$ -bit multiplier designs within minutes.

Verification of modern microprocessors is a complex task that requires a substantial allocation of resources. Despite significant progress in formal verification, the goal of complete verification of an industrial design has not been achieved. In this paper, we describe a current contribution of formal methods to the validation of modern x86 microprocessors at Centaur Technology. We focus on proving correctness of instruction implementations, which includes the decoding of an instruction, its translation into a sequence of micro-operations, any subsequent execution of traps to microcode ROM, and the implementation of these micro-operations in execution units. All these tasks are performed within one verification framework, which includes a theorem prover, a verified symbolic simulator, and SAT solvers. We describe the work of defining the needed formal models for both the architecture and micro-architecture in this framework, as well as tools for decomposing the requisite properties into smaller lemmas which can be automatically checked. We additionally cover the advantages and limitations of our approach. To our knowledge, there are no similar results in the verification of implementations of an x86 microprocessor.

In recent years, leading microprocessor companies have made huge investments to improve the reliability of their products. Besides expanding their validation and CAD tools teams, they have incorporated formal verification methods into their design flows. Formal verification (FV) engineers require extensive training, and FV tools from CAD vendors are expensive. At first glance, it may seem that FV teams are not affordable by smaller companies. We have not found this to be true. This paper describes the formal verification framework we have built on top of publicly-available tools. This framework gives us the flexibility to work on myriad different problems that occur in microprocessor design.

The advanced encryption standard (AES), approved by National Institute of Standards and Technology, specifies a cryptographic algorithm that can be used to protect electronic data. The next generation of Intel micro-processor introduces a set of instructions known as AES-NI, that promises multi-folded acceleration of the AES encryption and decryption process. In this paper, we report about the formal verification of hardware support for these new instructions. The verification is based on use of symbolic trajectory evaluation that lies at the base of formal verification methodology used by Intel Corporation. To our knowledge, this is the first formal verification of AES hardware support.

Variable reordering is the main approach to minimize the size of Ordered Binary Decision Diagrams. But despite the huge effort spent, up to now, to design different reordering heuristics, their performance often does not meet the needs of the applications. In many OBDD-based computations, the time cost for reordering dominates the time spent by the computation itself. There are some known approaches for accelerating the reordering by taking advantage of structural properties of OBDDs and functions represented. In this paper, we propose a reordering method that exploits application specific information. The main idea is to drive the reordering process by the computation. This effects an acceleration of the whole computation rather than of the reordering only. The power of the approach is illustrated by speeding up forward traversal of finite state machines.

The use of Ordered Binary Decision Diagrams (OB-DDs) as a representation of Boolean functions brought essential progress in many different applications. The optimization of the OBDD-size by the choice of the variable ordering is known to be NP-hard. The known heuristics for finding an initial ordering and for reordering still have insufficient performance. Rudell's sifting is one of the most successful reordering algorithms that is application independent and can be used dynamically. In this paper, we propose a method based on some communication complexity considerations that improves the time performance of the sifting. The main idea is to restrict the reordering of variables to blocks that are determined according to readily computable OBDD-measure. Experimental comparison of the proposed block-restricted sifting with the original algorithm shows a speed-up by factor two without any loss in the final size.

Reduced ordered binary decision diagrams (OBDD's) are nowadays the state-of-the-art representation scheme for Boolean functions in Boolean manipulation. Recent results have shown that it is possible to use the more general concept of free binary decision diagrams (FBDD's) without giving up most of the useful computational properties of OBDD's, but possibly reducing the space requirements considerably. The amount of space reduction depends essentially on the shape of so-called FBDD-types the Boolean manipulation in terms of FBDD's is based on. Here, we propose some heuristics for deriving tree-like FBDD-types from given circuit descriptions. The experimental results we obtained clearly demonstrate that the FBDD-approach is not only of theoretical interest, but also of practical usefulness even in the ease of using merely such simple-structured tree-based FBDD-types as produced by the investigated heuristics.

It is well-known that the size of an ordered binary decision diagram (OBDD) may depend crucially on the order in which the variables occur. In the paper, we describe an implementation of an output-efficient algorithm that transforms an OBDD P representing a Boolean function f with respect to one variable ordering /spl pi/ into an OBDD Q that represents f with respect to another variable ordering /spl sigma/. The algorithm runs in average time O(|P/spl par/Q|) and requires O(|P|+|Q|) space. The importance of the algorithm is demonstrated by means of experimental results on basically two different applications. In one of them, the algorithm is used merely once. Such transformations are needed to test equivalence or to perform synthesis on OBDD's in which variables appear in different orders. The other application shows a way how to decrease the size of intermediate OBDD representations of a given circuit in the course of its symbolic simulation. Here, the algorithm is used dynamically, whenever the size of the manipulated OBDD's becomes too large.

We present the concept of TBDD's which considerably enlarges the class of Boolean functions that can be efficiently manipulated in terms of OBDD's. It extends the idea of using domain trans-formations, which is well-known in many areas of mathematics, physics, and technical sciences, to the context of OBDD-based Boolean function manipulation in CAD: Instead of working with the OBDD-representation of a function f, TBDD's allow working with an OBDD-representation of a suited cube transformed version of f. Besides of giving some theoretical insights into the new concept, we investigate in some detail cube transformations which are based on complete types. We show that such TBDD-representations can be derived similarly as OBDD-representations, give evidence of the practical importance of such TBDD's by presenting very small-size TBDD-representations of the hidden weighted bit functions