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Pramode Ranjan Bhattacharjee

dblp:34/5750 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1991
0000-0001-8120-5443ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 97% Integrated circuit design · 3%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.021991
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming · IEEE Trans. Computers 1991
A novel design of sequential network to facilitate fault detection · Proc. IEEE 1987
Electronic design automation › hardware verification and test › fault modeling
bridging fault
0.011991
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming · IEEE Trans. Computers 1991
Electronic design automation › hardware verification and test
fault modeling
0.011991
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming · IEEE Trans. Computers 1991
Electronic design automation › hardware verification and test
test generation
0.011991
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming · IEEE Trans. Computers 1991
Electronic design automation › hardware verification and test
fault detection
0.011987
A novel design of sequential network to facilitate fault detection · Proc. IEEE 1987
Electronic design automation › hardware verification and test › fault detection
stuck-at fault detection
0.011987
A novel design of sequential network to facilitate fault detection · Proc. IEEE 1987
Integrated circuit design
digital circuit design
0.011987
A novel design of sequential network to facilitate fault detection · Proc. IEEE 1987

Methods — techniques the papers use, named apart from their topics

pseudo-boolean programming · 0.0boolean algebra · 0.0logic gate insertion · 0.0additional observed outputs · 0.0
YearPublicationVenuePosition
1991 Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming
abstract
An attempt is made to demonstrate that the problem of complete test set generation is amenable to the problem of pseudo-Boolean programming. For this purpose, various types of faults, viz., single faults, multiple faults, and bridging faults, are considered. The key issue is to obtain logical expressions for the primary output line in terms of different faulty internal nodes to find real transforms. Using standard rules, the real transforms of a Boolean function can be obtained directly without any algebraic manipulation.>
Pramode Ranjan Bhattacharjee, Sanjoy Kumar Basu, Jogesh Chandra Paul
IEEE Trans. Computers1
1987 A novel design of sequential network to facilitate fault detection
abstract
This technical letter reports the development of a novel design for a sequential network in order to facilitate the single stuck-at fault detection problem. This has been achieved by the use of AND, OR, and NOT logic gates and by inserting additional observed outputs.
Pramode Ranjan Bhattacharjee, Sanjoy Kumar Basu, Jogesh Chandra Paul
Proc. IEEE1
1986 Complete test-set generation for bridging faults in combinational-logic circuits
Sanjoy Kumar Basu, Jogesh Chandra Paul, Pramode Ranjan Bhattacharjee
Inf. Sci.3