Demo Data from VLDB 2026 / reviewers in the wild / expert
Quentin L. Meunier
dblp:34/8464
· DBLP profile ↗
6ranked-venue papers
4as first author
3since 2021 · last 2023
0000-0001-8848-8079ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 1 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
3 papers |
Hardware security and side channels · 89% Cryptographic primitives and cryptanalysis · 11% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 6 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › side-channel countermeasures › masking
masking verification |
0.7 | 1 | 2023 | LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions · IEEE Trans. Software Eng. 2023 |
Hardware security and side channels
side-channel attack |
0.7 | 1 | 2023 | LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions · IEEE Trans. Software Eng. 2023 |
Hardware security and side channels › side-channel countermeasures
masking |
0.6 | 2 | 2023 | Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions · IEEE Trans. Software Eng. 2023 |
Hardware security and side channels › microarchitectural side channel
microarchitectural leakage modeling |
0.6 | 1 | 2022 | ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Cryptographic primitives and cryptanalysis
finite field arithmetic |
0.4 | 1 | 2020 | Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Hardware security and side channels
side-channel countermeasures |
0.4 | 1 | 2020 | Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020 |
Methods — techniques the papers use, named apart from their topics
formal verification · 1.4static single assignment · 0.9polynomial interpolation · 0.9boolean masking · 0.9symbolic verification · 0.7substitution method · 0.7leakage test vectors · 0.6RTL modeling · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | VerifMSI: Practical Verification of Hardware and Software Masking Schemes ImplementationsabstractInternational audience Quentin L. Meunier, Abdul Rahman Taleb |
SECRYPT | 1 |
| 2023 | LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic ExpressionsabstractSide-channel attacks are a powerful class of attacks targeting cryptographic devices. Masking is a popular protection technique to thwart such attacks as it can be theoretically proven secure. However, correctly implementing masking schemes is a non-trivial task and error-prone. If several techniques have been proposed to formally verify masked implementations, they all come with limitations regarding expressiveness, scalability or accuracy. In this work, we propose a symbolic approach, based on a variant of the classical substitution method, for formally verifying arithmetic and boolean masked programs. This approach is more accurate and scalable than existing approaches thanks to a careful design and implementation of key heuristics, algorithms and data structures involved in the verification process. We present all the details of this approach and the open-source tool calledLeakageVerifwhich implements it as a python library, and which offers constructions for symbolic expressions and functions for their verification. We compareLeakageVerifto three existing state-of-the-art tools on a set of 46 masked programs, and we show that it has very good scalability and accuracy results while providing all the necessary constructs for describing algorithmic to assembly masking schemes. Finally, we also provide the set of 46 benchmarks, namedMaskedVerifBenchsand written for comparing the different verification tools, in the hope that they will be useful to the community for future comparisons. Quentin L. Meunier, Etienne Pons, Karine Heydemann |
IEEE Trans. Software Eng. | 1 |
| 2022 | ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal VerificationabstractSide-channel attacks are powerful attacks for retrieving secret data by exploiting physical measurements, such as power consumption or electromagnetic emissions. Masking is a popular countermeasure as it can be proven secure against an attacker model. In practice, software-masked implementations suffer from a security reduction due to a mismatch between the considered leakage sources in the security proof and the real ones, which depend on the microarchitecture. We propose ARMISTICE, a framework for formally verifying the absence of leakage in first-order masked implementations taking into account modeled microarchitectural sources of leakage. As a proof of concept, we present the modeling of an Arm Cortex-M3 core from its RTL description and leakage test vectors, as well as the modeling of the memory of an STM32F1 board, exclusively using leakage test vectors. We show that, with these models, ARMISTICE pinpoints vulnerable instructions in real-world masked implementations and helps the design of masked software implementations which are practically secure. Arnaud de Grandmaison, Karine Heydemann, Quentin L. Meunier |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2020 | Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial InterpolationabstractSide-channel attacks are amongst the major threats for embedded systems and IoT devices. Masking is one of the most used countermeasure against such attacks, but its application remains a difficult process. We propose a target-independent approach for applying a first-order Boolean masking countermeasure during compilation, on the static single assignment (SSA) form. Contrary to the state-of-the art automated approaches that require to simplify the control flow of the input program, our approach supports regular control-flow program structures. Moreover, our compiler is the first to automatically mask table lookups using a polynomial interpolation approach. We also present new optimizations to speedup the evaluation of polynomials: we reduce the number of terms of the polynomial, and we accelerate finite-field multiplication. We show that our approach is faster than the standard masked table approach with mask refresh after each access, with speedups up to ×2.4 in our experiments. Finally, using a formal verification approach, we show that the compiled machine code is secure, i.e., that all intermediate computations are statistically independent of the secrets. Nicolas Belleville, Damien Couroussé, Karine Heydemann, Quentin L. Meunier, Inès Ben El Ouahma |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 2010 | Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies
Quentin L. Meunier, Frédéric Pétrot |
J. Parallel Distributed Comput. | 1 |
| 2010 | Hardware/software support for adaptive work-stealing in on-chip multiprocessor
Quentin L. Meunier, Frédéric Pétrot, Jean-Louis Roch |
J. Syst. Archit. | 1 |