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Mark Taparauskas

dblp:34/910 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing
channel routing
0.011992
Geometric compaction on channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation
physical design
0.011992
Geometric compaction on channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › physical design
routing
0.011992
Geometric compaction on channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › physical design › routing
via minimization
0.011992
Geometric compaction on channel routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992

Methods — techniques the papers use, named apart from their topics

topological sorting · 0.0contour-following · 0.0
YearPublicationVenuePosition
1992 Geometric compaction on channel routing
abstract
A channel compaction algorithm incorporating via minimization and lateral via shifting is discussed. Bump propagation from the center of vias is the crucial phenomenon preventing compaction results from attaining the lower bound. Via minimization reduces the sources of the bumps, and lateral via shifting splits the critical paths which dominate the height of the channel. The authors adopt a contour-following approach as the basic operation to compact and straighten each wire. The sequence of the wires is determined by a topological sorting algorithm which also resolves any ordering conflicts by splitting the wires. The authors show the effectiveness of via minimization and shifting in reducing channel routing area. An improvement of up to 22.9% over one-dimensional compaction has been observed. Experiments on various solutions of Deutsch's difficult example indicate no significant relationship between the compacted channel height and the number of tracks in the routing solution.>
Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4