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Network Function Visualization (NFV) is becoming a new networking architecture for telecom carriers. NFV achieves network functions with software and commercial off the shelf (COTS) servers instead of dedicated hardware. While the software-based approach is expected to reduce costs, it could cause performance issues. CPU-FPGA tightly coupled architectures may be available in COTS servers in the near future. This paper proposes accelerating NFV application leveraging such a CPU-FPGA architecture. The proposed method of acceleration uses a data plane development kit (DPDK) ring queue, which is often used in network software, as the communication interface between the FPGA and CPU. We propose two optimizations for ring operation and table lookup operation to efficiently use the bus between FPGA and CPU. We evaluated the proposed method with an actual CPU+FPGA based platform, and an NFV application, i.e., vCPE. The results revealed that the evaluation system could accommodate 2 × 40-GbE Internet traffic, and could increase capacity as a vCPE server by x1.33.

IoT(Internet of Things), which collects various data in real world and analyzes values from collected data is one of good methods to help solve such serious problems and to construct efficient social systems. Meanwhile, since collected data is very complicated and has huge size, it takes a long time to collect and analyze “Complicated Big data”. Then, efficient computer systems and efficient network systems are necessary. Integration of heterogeneous computing and 5G network is one of the best platforms to provide complex IoT systems and services. In this paper, first, a reason why complex IoT systems require high performance hetero computing and high-speed communication systems like as 5G is presented. In the next, some use cases of IoT systems infrastructures empowered by hetero computing are also introduced.

In this paper, a legend story to develop CAD algorithms and CAD/EDA tools for NEC's in-house use is described. About 30 years ago, since there are few commercial CAD tools, ICT vendors had to develop their own CAD tools to enhance the performance of their systems in a short time. Prof. Goto developed several important algorithms for CAD tools and managed to develop many excellent in-house CAD tools. The tools made by him and his apprentices have designed many VLSI/ASIC for NEC's innovative computers and communication systems to enrich our daily lives.

Recent advances in photonics technologies have made optical interconnection network an attractive option for computing systems from high-performance computers and data centers to automobiles and cellphones. Optical interconnection network promises ultra-high bandwidth, low latency, and great energy efficiency to alleviate the inter-rack, intra-rack, intraboard, and intra-chip communication bottlenecks in multiprocessor systems. Silicon-based photonics technologies piggyback onto developed silicon fabrication processes to provide viable and cost-effective solutions. Both industry and academia have invested significant efforts to develop and commercialize optical interconnection network technologies. This paper reviews the latest progresses and provides insights into the challenges and future developments.

We revisit RDMA-based rendezvous protocols in MPI in the context of cluster computer with RDMA-capable HCA and many-core processors, and propose two improved protocols. The conventional sender-initiate rendezvous protocols cause costly processor-device communications via PCI bus on detecting completion of RDMA transfer. The conventional receiver-initiate rendezvous protocols need to send extra control messages when a value of the memory-slot to poll in the receive buffer has the same value as the send buffer. The first proposed protocol implements polling on a memory-slot in the receive buffer to eliminate the processor-device communications. The second proposed protocol randomizes the value of the memory-slot to poll to reduce extra control messages. We have evaluated the proposed protocols using micro-benchmarks and NAS Parallel Benchmarks. One of the proposed protocols has a benefit compared to the conventional protocols. And the second proposed protocol reduces the execution time by up to 11.14% compared to the first protocol.

In this paper, we propose a novel mapping method for FPGA with dual-output LUT based logic elements (LEs), aiming for power reduction. Recently, a new kind of LE-Adaptive Logic Module (ALM), which contains a dual-output fracturable LUT instead of traditional single-output K-LUT, is used in Altera's high-end FPGA products to obtain a good trade-off between area and delay. To map a design to ALMs, we introduce a LUT-merging step after K-LUT technology mapping, where the LUTs are merged into ALMs. We propose a max-weight matching based method for the LUT-merging, trying to reduce the number of used ALMs and meanwhile reduce power consumption. Experimental results show that, compared with a previous LUT-merging method for area-optimization, though resulting in a little more ALMs, our low power LUT-merging method improves the power by 7.48%.

We propose a method to analysis the delay of the sub-path on fabricated chips by the several path-delay tests. In recent years, the process variation causes the timing faults. To detect the faults, the path-delay test is one of the most promising methods. The path-delay test checks whether the signals along the target paths in fabricated LSIs are propagated under the specified frequency. In this paper, we propose a method to analysis the delay value of the paths with path-delay tests. The proposed method consists of 1) path-delay tests for several paths, 2) estimation of the sub-path of the testing paths, and 3) expansion of the remaining path according to the resultant estimations. We confirm that our proposed method calculates the delay with about 0.05% errors empirically.

Multi-FPGA systems are widely used for rapid prototyping and logic verification of VLSIs. To implement a huge logic circuit in a multi-FPGA system, the circuit needs to be partitioned into multiple FPGAs. Because of the limited interconnection resources between FPGAs, time-multiplexed I/Os are used for inter-FPGA connections. Due to the large delay of time-multiplexed I/Os, inter-FPGA connections strongly affect the system performance. In this paper, we extend an ILP-based optimization method of the inter-FPGA connections to improve the system performance. Our method uses both a normal I/O and a time-multiplexed I/O, and decides whether each inter-FPGA signal is transferred by a time-multiplexed I/O or not. Our extended method improves the system performance considering the variation of the amount of interconnection resources, and the variation of the number of inter-FPGA signals, from an FPGA pair to another FPGA pair. Experiments showed that our method improved the circuit performance on a 4-FPGA system by 26.4% compared with a conventional method, on average.

Due to the limited device capacity of an FPGA, multi-FPGA systems are used to verify huge state-of-the-art circuits. In the case, the number of I/O signals of each sub-circuit implemented in an FPGA tends to exceed the number of I/O-pins of the FPGA. To resolve the problem, time-multiplexed I/Os are used. Each of time-multiplexed I/Os is shared by multiple I/O signals of a sub-circuit by time-division. Since timemultiplexed I/Os introduce large delay, we propose algorithms which obtain the optimal number of required I/O-pins under the given timing constraint by choosing signals to be time-multiplexed.

This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve sub-optimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500 MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days.

For multi-FPGA systems, the limitation of the number of FPGA I/O-pins is one of the most critical issues. Using time-multiplexed I/Os eases the limitation. While, a signal path through n time-multiplexed I/Os makes the system clock period n + 1 times longer at most. To capture this feature, we introduce a new cost total cut-hopcount. Under the total cut-hopcount, we propose a performance-driven bipartitioning method VIOP. VIOP combines three algorithms, such that i) min-cut partitioning, ii) coarse performance-driven partitioning, and iii) fine performance-driven partitioning. For min-cut and coarse performance-driven partitioning, we employ well-known bipartitioning algorithms CLIP-FM and DUBA, respectively. For fine performance-driven partitioning, we propose a partitioning algorithm CAVP. By VIOP, the average cost was improved by 11.5% compared with the state-of-the-art algorithms

This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".

Proposes a hardware/software co-simulation environment using an RTL (register transfer level) simulator with a software language interface. The proposed simulation environment introduces the "operating system interface" (OSIF), which invokes system calls in the OS on the simulation platform to execute application software. The OSIF consists of data adaption facility and function correspondence management allowing it to cooperate with the OS of the simulation platform. We show the results of experiments with an R3000-compatible processor model. This environment verified our processor model with SPEC benchmarks that require various OS services. For example, with the Lisp interpreter program li, our detailed RTL description for the core part of R3000 was simulated only within 20 hours on a 109 MIPS workstation.

Abstract|This paper presents a new logic partitioning method for optimizing large scale circuits.The proposed method partitions a given circuit into transitive fanindisjoint sub-circuits by matrix operations, so that various optimization methods can be applied to each partitioned sub-circuit instead of the whole circuit.Experimental results show that the proposed method achieves high-quality design comparable to the one optimized for the whole circuits, with much shorter time(1/20).Thus, the circuits with over 10,000 gates can be optimized by the proposed partitioning.

Abstract| This paper presents a novel method for logic minimization in large-scale multi-level networks.It accomplishes its great reductions on the basis of multi-signal implications and the relationships among these implications.Both are handled on a transitive implication graph, proposed in this paper, which realizes high-speed, high-quality minimization.This proposed method holds great promise for the achievement of an interactive logic design environment for large-scale networks.