Demo Data from VLDB 2026 / reviewers in the wild / expert
John Lapeyre
dblp:342/7948
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Emerging computing paradigms · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › domain-specific compilation
quantum compilation |
0.7 | 1 | 2023 | CaQR: A Compiler-Assisted Approach for Qubit Reuse through Dynamic Circuit · ASPLOS (3) 2023 |
Emerging computing paradigms
quantum computer architecture |
0.7 | 1 | 2023 | CaQR: A Compiler-Assisted Approach for Qubit Reuse through Dynamic Circuit · ASPLOS (3) 2023 |
Emerging computing paradigms › quantum computer architecture › quantum compilation
qubit reuse |
0.7 | 1 | 2023 | CaQR: A Compiler-Assisted Approach for Qubit Reuse through Dynamic Circuit · ASPLOS (3) 2023 |
Emerging computing paradigms
quantum computing |
0.2 | 1 | 2023 | CaQR: A Compiler-Assisted Approach for Qubit Reuse through Dynamic Circuit · ASPLOS (3) 2023 |
Methods — techniques the papers use, named apart from their topics
compiler-assisted optimization · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | CaQR: A Compiler-Assisted Approach for Qubit Reuse through Dynamic CircuitabstractQuantum measurement is important to quantum computing as it extracts out the outcome of the circuit at the end of the computation. Previously, all measurements have to be done at the end of the circuit. Otherwise, it will incur significant errors. But it is not the case now. Recently IBM starts supporting dynamic circuit through hardware (instead of software by simulator). With mid-circuit hardware measurement, we can improve circuit efficacy and fidelity from three aspects: (a) reduced qubit usage, (b) reduced swap insertion, and (c) improved fidelity. We demonstrate this using real-world applications Bernstein Verizani on real hardware and show that circuit resource usage can be improved by 60%, and circuit fidelity can be improved by 15%. We design a compiler-assisted tool that can find and exploit the tradeoff between qubit reuse, fidelity, gate count, and circuit duration. We also developed a method for identifying whether qubit reuse will be beneficial for a given application. We evaluated our method on a representative set of important applications. We can reduce resource usage by up to 80% and improve circuit fidelity by up to 20%. Yuwei Jin, Yan-Hao Chen, Suhas Vittal, Kevin Krsulich, Lev S. Bishop, John Lapeyre, Ali Javadi-Abhari, Eddy Z. Zhang |
ASPLOS (3) | 7 |