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Krishnan Gosakan

dblp:342/8196 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2023
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 95% Storage systems · 5%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › virtual memory
address translation
0.712023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023
Memory systems › virtual memory management
page mapping
0.712023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023
Memory systems › memory management › virtual memory › address translation
TLB
0.712023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023
Memory systems › memory management › virtual memory
TLB reach
0.712023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023
Memory systems › memory management
virtual memory
0.712023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023
Storage systems › storage management › storage allocation › fragmentation management
defragmentation
0.212023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023
Memory systems
memory management
0.212023
Mosaic Pages: Big TLB Reach with Small Pages · ASPLOS (3) 2023

Methods — techniques the papers use, named apart from their topics

hashing · 0.7gem5 simulation · 0.7
YearPublicationVenuePosition
2023 Mosaic Pages: Big TLB Reach with Small Pages
abstract
The TLB is increasingly a bottleneck for big data applications. In most designs, the number of TLB entries are highly constrained by latency requirements, and growing much more slowly than the working sets of applications. Many solutions to this problem, such as huge pages, perforated pages, or TLB coalescing, rely on physical contiguity for performance gains, yet the cost of defragmenting memory can easily nullify these gains. This paper introduces mosaic pages, which increase TLB reach by compressing multiple, discrete translations into one TLB entry. Mosaic leverages virtual contiguity for locality, but does not use physical contiguity. Mosaic relies on recent advances in hashing theory to constrain memory mappings, in order to realize this physical address compression without reducing memory utilization or increasing swapping. This paper presents a full-system prototype of Mosaic, in gem5 and modified Linux. In simulation and with comparable hardware to a traditional design, mosaic reduces TLB misses in several workloads by 6-81%. Our results show that Mosaic’s constraints on memory mappings do not harm performance, we never see conflicts before memory is 98% full in our experiments — at which point, a traditional design would also likely swap. Once memory is over-committed, Mosaic swaps fewer pages than Linux in most cases. Finally, we present timing and area analysis for a verilog implementation of the hashing function required on the critical path for the TLB, and show that on a commercial 28nm CMOS process; the circuit runs at a maximum frequency of 4 GHz, indicating that a mosaic TLB is unlikely to affect clock frequency.
Krishnan Gosakan, Jaehyun Han, William Kuszmaul, Ibrahim N. Mubarek, Nirjhar Mukherjee, Karthik Sriram, Guido Tagliavini, Evan West, Michael A. Bender, Abhishek Bhattacharjee, Alexander Conway 0001, Martin Farach-Colton, Jayneel Gandhi, Rob Johnson 0001, Sudarsun Kannan, Donald E. Porter
ASPLOS (3)1