This paper proposes a high-quality 3D placement algorithm to determine the positions of standard cells and inter-die vias to optimize wirelength considering multiple manufacturing technologies for different dies. The algorithm consists of three major novel techniques: (1) a multi-technologies weighted-average (MTWA) wirelength model, (2) a weighted inter-die-connection cost controlling the net-degree distribution of the cut set, and (3) a via-cell co-optimization technique to further improve the quality of placement solutions. Compared with the winners at the 2022 CAD Contest at ICCAD on 3D Placement with D2D Vertical Connections, our placer achieves the best results for all nontrivial cases.

The dramatic growth of hardware attacks and the lack of security-concern solutions in design tools lead to severe security problems in modern IC designs. Although many existing countermeasures provide decent protection against security issues, they still lack the global design view with sufficient security consideration in design time. This paper proposes a security-aware framework against Trojan insertion, frontside probing, and fault injection attacks at the design stage. The framework consists of two major techniques: (1) a large-scale shielding method that effectively covers the exposed areas of assets and (2) a cell-movement-based method to eliminate the empty spaces vulnerable to Trojan insertion. Experimental results show that our framework effectively reduces the vulnerability of these attacks and achieves the best overall score compared with the top-3 teams in the 2022 ACM ISPD Security Closure of Physical Layouts Contest.