We introduce Mixture-of-Trees (MoT), a novel framework that integrates sparse expert activation with structured tree-based reasoning for efficient LLM inference. MoT employs a learned gating mechanism to selectively activate only the most relevant expert reasoning trees for each problem, where experts use models of varying capacities based on task complexity. The framework features three key innovations: (1) sparse expert activation through unified gating networks, (2) specialized expert trees that leverage domain-specific expertise while optimizing the quality-efficiency trade-off, and (3) collaborative debate mechanisms for conflicting solutions. Additionally, MoT includes a shared baseline tree with early stopping—activated experts perform lightweight validation and terminate early when confidence is high. Experiments across five benchmarks (GSM8K, MATH, AIME 2024, MMLU, HotpotQA) show that MoT achieves 2-7 percentage point accuracy improvements while reducing LLM calls by 37-40% compared to existing multi-path methods.

Large Language Models (LLMs) are achieving unprecedented performance across diverse tasks, benefiting from autoregressive generation. However, this left-to-right decoding paradigm inherently limits contextual understanding quality. Diffusion-based LLMs (dLLMs) offer a promising alternative by iteratively refining sequences via denoising, enabling stronger bidirectional context modeling and improved generation quality. However, dLLMs face two main challenges: redundant computation and memory overhead in multi-step denoising, and excessive inference cost from over-denoising under fixed-step schedules. To address these issues, we propose dLLM-OPU, an FPGA overlay processor to accelerate dLLMs. Our solution features two key innovations: (1) a Region-Adaptive Caching for Dynamic Column Sparsity Framework that exploits temporal locality for selective recomputation without model retraining, and (2) a Token Entropy-based Early Stopping strategy that dynamically terminates the denoising process based on token-level convergence metrics. We implement these innovations through a specialized sparse processing element (PE) array that maximizes top-k sparsity utilization by minimizing idle cycles via row-column concatenation, complemented by an efficient cache management system that reduces memory access latency and a flexible entropybased decoding unit. Implemented on a U200 FPGA, dLLM-OPU achieves $2.2 \times-5.1 \times$ speedup and $7.6 \times-20.3 \times$ energy efficiency over RTX4090 in LLaDA.

Area and power optimization of Fixed Polarity Reed–Muller (FPRM) circuits has received a lot of attention. Polarity optimization for FPRM circuits is essentially a binary multi-objective optimization problem. However, the existing area and power optimization approaches for FPRM logic circuits rarely produce a frontier and a greater number of Pareto optimal solutions . In this paper, a Multi-strategy Multi-objective Artificial Bee Colony (MMABC) algorithm is proposed to solve the binary multi-objective optimization problem. The main innovation of MMABC can be summarized as follows: a flexible foraging behavior strategy for employed bees is proposed to improve the searching ability of the algorithm; a genetic retention evolution for onlooker bees is proposed to improve the quality of the population; an efficient transform strategy is proposed to help the algorithm to jump out the local optimal and increase convergence speed. Moreover, we propose an area and power optimization approach for FPRM logic circuits, which uses the MMABC to search for the polarities (i.e., Pareto optimal solutions) with smaller area and lower power. Experimental results demonstrated the effectiveness and superiority of our approach in optimizing area and power of FPRM logic circuits.