FPGA-based acceleration has been explored to address performance challenges in architectures incorporating federated learning (FL) and homomorphic encryption (HE). However, model updates, which involve HE, are infrequent in FL applications; thus, static allocation of FPGA resources for HE can lead to inefficiency. In response, this paper presents a work-in-progress FPGA-based FL accelerator that leverages dynamic partial reconfiguration to accelerate HE operations flexibly.

Timing control while preserving determinism is often a key requirement for ensuring the safety and correctness of distributed cyber-physical systems (CPS). Discrete-event (DE) systems provide a suitable model of computation (MoC) for time-sensitive distributed CPS. The high-level architecture (HLA) is a useful tool for the distributed simulation of DE systems, but its techniques can be adapted for implementing distributed CPS. However, HLA incurs considerable overhead in network messages conveying timing information between the distributed nodes and the centralized run-time infrastructure (RTI). This paper gives a novel approach and implementation that reduces such network messages while preserving DE semantics. An evaluation of our runtime demonstrates that our approach significantly reduces the volume of messages for timing information in HLA.