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Angana Nath

dblp:347/3116 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 87% Reconfigurable computing and FPGAs · 13%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › post-quantum cryptography
lattice-based cryptography
0.712023
Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications · IEEE Trans. Computers 2023
Cryptographic primitives and cryptanalysis
post-quantum cryptography
0.712023
Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications · IEEE Trans. Computers 2023
Integrated circuit design
digital circuit design
0.712023
Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications · IEEE Trans. Computers 2023
Integrated circuit design › digital circuit design › arithmetic circuit design
modular multiplier
0.712023
Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications · IEEE Trans. Computers 2023
Reconfigurable computing and FPGAs
FPGA implementation
0.212023
Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications · IEEE Trans. Computers 2023

Methods — techniques the papers use, named apart from their topics

tensor representation · 1.3polynomial multiplication · 1.3
YearPublicationVenuePosition
2023 Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications
abstract
Modulo polynomial multiplication is an essential mathematical operation in the area of finite field arithmetic. Polynomial functions can be represented as tensors, which can be utilized as basic building blocks for various lattice-based post-quantum cryptography schemes. This paper presents a tensor-based novel modulo multiplication method for multivariate polynomials over$GF(2^{m})$and is realized on the hardware platform (FPGA). The proposed method consumes$6.5\times$less power and achieves more than$6\times$speedup compared to other contemporary single variable polynomial multiplication implementations. Our method is embarrassingly parallel and easily scalable for multivariate polynomials. Polynomial functions of nine variables, where each variable is of degree 128, are tested with the proposed multiplier, and its corresponding area, power, and power-delay-area product (PDAP) are presented. The computational complexity of single variable and multivariate polynomial multiplications are$O(n)$and$O(np)$, respectively, where$n$is the maximum degree of a polynomial having$p$variables. Due to its high speed, low latency, and scalability, the proposed modulo multiplier can be used in a wide range of applications.
Bikram Paul, Angana Nath, Srinivasan Krishnaswamy, Jan Pidanic, Zdenek Nemec, Gaurav Trivedi
IEEE Trans. Computers2