Superconducting quantum systems rely on microwave control paths that transform circuit-derived intent into qubit-facing waveform execution. Yet this radio-frequency (RF) control boundary is typically treated implicitly: compilation derives valid pulse-level intent, while hardware studies focus on analog behavior or downstream gate performance. As a result, cross-layer mismatches among intended control, tile operating state, and realized waveform remain underspecified, even though they can directly affect pulse fidelity, timing structure, and multi-channel coordination. In this paper, we present CRISP, a control-boundary framework for checking consistency among IntendedControl, TileState, and RealizedControl. CRISP introduces a behavioral RF-tile abstraction that models gain, phase distortion, bandwidth limitation, delay, and ringing/settling, and evaluates three pairwise consistency relations together with sequence-aware checks. Across five tile-state regimes, CRISP shows that nominal behavior can remain fully consistent while distorted states trigger distinct failure signatures, including up to 8 intended-to-realized failures, 4 intended-to-state failures, and 5 sequence violations. Under controlled sequence-stress extensions, CRISP further isolates timing drift from 9 ns to 20 ns, illegal overlap from 2 ns to 14 ns, and explicit channel mismatch. These results show that correctness at the RF control boundary is fundamentally relational rather than purely local.

Quantum computing requires effective error correction strategies to mitigate noise and decoherence. Quantum Low-Density Parity-Check (QLDPC) codes have emerged as a promising solution for scalable Quantum Error Correction (QEC) applications by supporting constant-rate encoding and a sparse parity-check structure. However, decoding QLDPC codes via traditional approaches such as Belief Propagation (BP) suffers from poor convergence in the presence of short cycles. Machine learning techniques like Graph Neural Networks (GNNs) utilize learned message passing over their node features; however, they are restricted to pairwise interactions on Tanner graphs, which limits their ability to capture higher-order correlations. In this work, we propose HyperNQ, the first Hypergraph Neural Network (HGNN)- based QLDPC decoder that captures higher-order stabilizer constraints by utilizing hyperedges-thus enabling highly expressive and compact decoding. We use a two-stage message passing scheme and evaluate the decoder over the pseudo-threshold region. Below the pseudo-threshold mark, HyperNQ improves the Logical Error Rate (LER) up to 84% over BP and 50% over GNN-based strategies, demonstrating enhanced performance over the existing state-of-the-art decoders.

Quantum circuit execution often requires transpilation into hardware-compatible instructions, which can significantly alter the original design, making equivalence checking essential. However, existing approaches struggle with scalability and computational overhead. In this paper, we present ZXNet, a transformative framework for quantum circuit equivalence checking using $\mathbf{Z X}$ calculus-based graph abstractions. Leveraging graph neural networks, ZXNet captures complex equivalence patterns by integrating critical local and global circuit features. ZXNet achieves 99.4% validation accuracy, and up to $62 \times$ speedup over state-of-the-art methods, furnishing improvements of 45.83% in scalability, 42.22% in per-qubit verification time, and 5.94% in accuracy, outperforming state-of-the-art approaches.

Quantum computing has proven to be capable of accelerating many algorithms by performing tasks that classical computers cannot. As quantum algorithms and implementations grow more complex, the need for rigorous circuit verification becomes critical, ensuring correct compilation and enhancing circuit fidelity through error correction and assertions. In this paper, we propose QuBEC, a Decision Diagram-based quantum equivalence checking approach, that requires less latency compared to existing techniques, while accounting for circuits with quantum error correction redundancy. QuBEC reduces verification time on benchmark circuits by up to 443×, while the number of Decision Diagram nodes required is reduced by up to 798.31×, compared to state-of-the-art strategies. The proposed QuBEC framework can contribute to the advancement of quantum computing by enabling faster and more efficient verification of quantum circuits, paving the way for the development of larger and more complex quantum algorithms.

Power side-channel (PSC) attacks exploit the dynamic power consumption of cryptographic operations to leak sensitive information about encryption hardware. Therefore, it is necessary to conduct a PSC analysis to assess the susceptibility of cryptographic systems and mitigate potential risks. Existing PSC analysis primarily focuses on postsilicon implementations, which are inflexible in addressing design flaws, leading to costly and time-consuming postfabrication design re-spins. Hence, presilicon PSC analysis is required for the early detection of vulnerabilities to improve design robustness. In this article, we introduce SCAR, a novel presilicon PSC analysis framework based on graph neural networks (GNNs). SCAR converts register-transfer level (RTL) designs of encryption hardware into control-data flow graphs (CDFGs) and use that to detect the design modules susceptible to side-channel leakage. Furthermore, we incorporate a deep-learning-based explainer in SCAR to generate quantifiable and human-accessible explanations of our detection and localization decisions. We have also developed a fortification component as a part of SCAR that uses large-language models (LLMs) to automatically generate and insert additional design code at the localized zone to shore up the side-channel leakage. When evaluated on popular encryption algorithms like advanced encryption standard (AES), RSA, and PRESENT, and postquantum cryptography (PQC) algorithms like Saber and CRYSTALS-Kyber, SCAR, achieves up to 94.49% localization accuracy, 100% precision, and 90.48% recall. Additionally, through explainability analysis, SCAR reduces features for GNN model training by 57% while maintaining comparable accuracy. We believe that SCAR will transform the security-critical hardware design cycle, resulting in faster design closure at a reduced design cost.

Quantum computers have demonstrated exponential speedup for certain computational tasks like integer factorization, molecular simulation, and machine learning, compared to the classical computers. One of the most challenging problems in quantum computing is quantum compilation, which involves the translation of a quantum circuit into a representation that adheres to the constraints imposed by the quantum hardware. However, this process of mapping the logical qubits to physical qubits incurs a significantly large search space, which needs to be analyzed to obtain the optimal mapping. A non-optimal mapping or compilation strategy introduces additional hardware overhead, thereby rendering inefficiency. Recently, researchers have proposed a technique to reduce the search space for efficient quantum compilation. However, this approach focuses on a generic solution involving only the physical architecture, and hence, as shown in our paper, often fails to incorporate the optimal solution in the reduced search space. To this end, we propose PERM and SGO (PAS), which, to the best of our knowledge, is the first quantum compilation strategy that facilitates a reduced search space comprising a more optimal solution in terms of additional CNOT gates compared to the existing technique. Our experimental evaluation using the MQT benchmarks demonstrates the efficacy of our approach, which furnishes up to 428x reduction compared to the unoptimized search space, and 57.1x reduction compared to existing research, while providing savings in terms of additional CNOT gates by up to 53.85%.