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Suprasad Mutalik Desai

dblp:349/0635 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
0009-0007-7999-4368ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Databases, data management, data science and information retrieval · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 91% Storage systems · 9%
Databases, data mining, and information retrieval
1 paper
Database system architecture and tuning · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Database system architecture and tuning
main-memory database
0.812024
An Examination of CXL Memory Use Cases for In-Memory Database Management Systems using SAP HANA · Proc. VLDB Endow. 2024
Memory systems › memory disaggregation
CXL memory
0.812024
An Examination of CXL Memory Use Cases for In-Memory Database Management Systems using SAP HANA · Proc. VLDB Endow. 2024
Memory systems
main memory database
0.812024
An Examination of CXL Memory Use Cases for In-Memory Database Management Systems using SAP HANA · Proc. VLDB Endow. 2024
Memory systems
memory disaggregation
0.812024
An Examination of CXL Memory Use Cases for In-Memory Database Management Systems using SAP HANA · Proc. VLDB Endow. 2024

Methods — techniques the papers use, named apart from their topics

workload characterization · 1.5performance analysis · 1.5
YearPublicationVenuePosition
2024 An Examination of CXL Memory Use Cases for In-Memory Database Management Systems using SAP HANA
abstract
CXL-based disaggregated memory systems offer options to expand the memory beyond the limits of a single server via cache-coherent memory expansion cards or memory pools. Especially, In-Memory Database Management Systems (IMDBMSs) can benefit from alleviating two critical constraints: (1) limited memory capacity in a server and (2) long restart time during failover to reload data to memory. However, the usage and effectiveness of CXL memory in enterprise-scale IMDBMSs has yet to be validated. In this work---for the first time---we investigate dynamic memory expansion employing commercial CXL memory devices for IMDBMSs. Our detailed performance analysis reveals that the performance impact of higher latency and lower memory bandwidth impact depends on the memory access patterns of data structures (cf. (1)). Additionally, we present the feasibility of CXL shared memory between servers to improve restart times during failover (cf. (2)). Our evaluation shows the effectiveness of CXL memory integrated into the SAP HANA Cloud IMDBMS. OLTP workloads have a negligible performance degradation while OLAP workloads have a wide range of performance degradation. CXL shared memory shows a 40% reduction of the restart time for TPC-H SF10 and 84% potential reduction for TPC-H SF100.
Minseon Ahn, Thomas Willhalm, Norman May, Donghun Lee 0001, Suprasad Mutalik Desai, Daniel Booss, Navneet Singh, Daniel Ritter 0001, Oliver Rebholz
Proc. VLDB Endow.5
2023 Elastic Use of Far Memory for In-Memory Database Management Systems
abstract
The separation and independent scalability of compute and memory is one of the crucial aspects for modern in-memory database systems (IMDBMSs) in the cloud. The new, cache-coherent memory interconnect Compute Express Link (CXL) promises elastic memory capacity through memory pooling. In this work, we adapt the well-known IMDBMS, SAP HANA, for memory pools by features of table data placement and operational heap memory allocation on far memory, and study the impact of the limited bandwidth and higher latency of CXL. Our results show negligible performance degradation for TPC-C. For the analytical workloads of TPC-H, a notable impact on query processing is observed due to the limited bandwidth and long latency of our early CXL implementation. However, our emulation shows it would be acceptably smaller with the improved CXL memory devices.
Donghun Lee 0001, Thomas Willhalm, Minseon Ahn, Suprasad Mutalik Desai, Daniel Booss, Navneet Singh, Daniel Ritter 0001, Oliver Rebholz
DaMoN4