Demo Data from VLDB 2026 / reviewers in the wild / expert
Junsun Choi
dblp:349/5053
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0000-2007-4937ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 50% Cloud and datacenter computing · 50% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › domain-specific accelerator
compression accelerator |
0.7 | 1 | 2023 | CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems · ISCA 2023 |
Cloud and datacenter computing › datacenter architecture
datacenter tax offload |
0.7 | 1 | 2023 | CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems · ISCA 2023 |
Methods — techniques the papers use, named apart from their topics
lossless compression · 0.7hardware-software co-design · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale SystemsabstractGeneral-purpose lossless data compression and decompression ("(de)compression") are used widely in hyperscale systems and are key "datacenter taxes". However, designing optimal hardware compression and decompression processing units ("CDPUs") is challenging due to the variety of algorithms deployed, input data characteristics, and evolving costs of CPU cycles, network bandwidth, and memory/storage capacities. Sagar Karandikar, Aniruddha N. Udipi, Junsun Choi, Joonho Whangbo, Jerry Zhao, Svilen Kanev, Edwin Lim, Jyrki Alakuijala, Vrishab Madduri, Sophia Shao, Borivoje Nikolic, Krste Asanovic, Parthasarathy Ranganathan |
ISCA | 3 |