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Archit Agarwal

dblp:349/8288 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0003-0380-1471ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Hardware security and side channels · 89% Cryptographic primitives and cryptanalysis · 11%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 100%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
microarchitectural attacks
0.812024
Levioso: Efficient Compiler-Informed Secure Speculation · DAC 2024
Hardware security and side channels
microarchitectural side channel
0.812024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre
0.812024
Levioso: Efficient Compiler-Informed Secure Speculation · DAC 2024
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack
0.812024
Levioso: Efficient Compiler-Informed Secure Speculation · DAC 2024
Hardware security and side channels › microarchitectural attacks
transient execution attack
0.812024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Processor architecture and microarchitecture
branch prediction
0.812024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Processor architecture and microarchitecture › speculative execution
secure speculation
0.812024
Levioso: Efficient Compiler-Informed Secure Speculation · DAC 2024
Processor architecture and microarchitecture
speculative execution
0.812024
Levioso: Efficient Compiler-Informed Secure Speculation · DAC 2024
Cryptographic primitives and cryptanalysis › block cipher cryptanalysis
AES key recovery
0.212024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024
Cryptographic primitives and cryptanalysis
symmetric cryptography
0.212024
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor · ASPLOS (3) 2024

Methods — techniques the papers use, named apart from their topics

compiler-informed speculation restriction · 2.3prediction history table manipulation · 1.5path history register manipulation · 1.5control-flow reconstruction · 1.5
YearPublicationVenuePosition
2024 Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
abstract
This paper introduces novel attack primitives that enable adversaries to leak (read) and manipulate (write) the path history register (PHR) and the prediction history tables (PHTs) of the conditional branch predictor in high-performance CPUs. These primitives enable two new classes of attacks: first, it can recover the entire control flow history of a victim program by exploiting read primitives, as demonstrated by a practical secret-image recovery based on capturing the entire control flow of libjpeg routines. Second, it can launch extremely high-resolution transient attacks by exploiting write primitives. We demonstrate this with a key recovery attack against AES based on extracting intermediate values.
Hosein Yavarzadeh, Archit Agarwal, Max Christman, Christina Garman, Daniel Genkin, Andrew Kwong, Daniel Moghimi, Deian Stefan, Mohammadkazem Taram, Dean M. Tullsen
ASPLOS (3)2
2024 Levioso: Efficient Compiler-Informed Secure Speculation
abstract
Spectre-type attacks have exposed a major class of vulnerabilities arising from speculative execution of instructions, the main performance enabler of modern CPUs. These attacks speculatively leak secrets that have been either speculatively loaded (seen in sand-boxed programs) or non-speculatively loaded (seen in constant-time programs). Various hardware-only defenses have been proposed to mitigate both speculative and non-speculative secrets via all potential transmission channels. However, limited program knowledge is exposed to the hardware and these solutions conservatively restrict the execution of all instructions that can potentially leak.
Ali Hajiabadi, Archit Agarwal, Andreas Diavastos, Trevor E. Carlson
DAC2