Decai Pan

dblp:349/9288 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
0009-0009-5273-1204ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › memory system microarchitecture
address generation
0.812024
PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis · DAC 2024
Electronic design automation
high-level synthesis
0.812024
PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis · DAC 2024
Electronic design automation › high-level synthesis › memory synthesis
memory partitioning
0.812024
PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis · DAC 2024

Methods — techniques the papers use, named apart from their topics

pattern morphing · 0.8integer linear programming · 0.8
YearPublicationVenuePosition
2024 PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis
abstract
Memory partitioning is a widely used technique to reduce access conflicts on multi-bank memory in high-level synthesis. Previous memory partitioning methods mainly focus on a given access pattern extracted from stencil applications. Restricted by the pattern shape, these methods are prone to sub-optimal bank numbers or large overhead on address generation. In this work, we propose a pattern-morphing-based memory partitioning method, PMP, that only requires reduced hyperplane families to achieve the minimal bank number. To reduce the side effect of extra data padding, an integer linear programming problem is formulated for pattern morphing. Compared to the previous hyperplane-based memory partitioning, the experimental results show that our approach could achieve the optimal partition factor while saving 22% in LUTs, 21% in FlipFlops, 10% in DSPs, and 40% in memory overhead, on average.
Dajiang Liu, Decai Pan, Xiao Xiong, Jiaxing Shang, Shouyi Yin
DAC2
2023 Optimizing Memory Allocation for Multi-Subgraph Mapping on Spatial Accelerators
abstract
Spatial accelerators enable the pervasive use of energy-efficient solutions for computation-intensive applications. In the mapping of spatial accelerators, a large kernel is usually partitioned into multiple subgraphs for resource constraints, leading to more memory accesses and access conflicts. To minimize the access conflicts, existing works either neglect the interference of multiple subgraphs or pay little attention to data's life cycle along the execution order. To this end, this paper proposes an optimized memory allocation approach for multi-subgraph mapping on spatial accelerators by constructing an optimization problem using Integer Linear Programming (ILP). The experimental results demonstrate that our work can find conflict-free solutions for most kernels and achieve 1.15× speedup, as compared to the state-of-the-art approach.
Decai Pan, Dajiang Liu, Xueliang Du
SYSTOR2