Software-defined networking (SDN) is recognized as a promising solution for the efficient management of numerous devices in the Internet of Things (IoT). To appropriately forward the incoming packets, SDN-enabled devices request the controller for traffic rules resulting in a significant delay. To avoid frequent communication with the controller and reducing the delay, these devices cache the rules as match action pairs in flow tables for a certain amount of time. This is referred to as rule caching. Flow tables are made of ternary content-addressable memories (TCAMs) capable of high-speed parallel lookup. Nonetheless, due to the high expenses and power consumption of TCAMs, flow tables have limited capacity and cannot store rules of all the users. Therefore, the assignment of limited flow tables is a challenge in IoT networks with a large number of users. In this article, we consider an SDN-enabled base station serving a set of users in a cell and is equipped with a finite-capacity flow table. We assume users' traffic obeys a bursty ON-OFF model and formulate the efficient allocation of flow table entries to users over time. It results in a mixed-integer nonlinear program. We introduce a change of variables that turns the problem into an integer linear program. This is still intractable and cannot support problems with large dimensions such as massive IoT networks. To handle its complexity, we design a time-efficient procedure with close-to-optimal performance. Finally, numerical results demonstrate the significant improvement achieved by the proposed scheme.

This paper formulates linear MMSE receivers that are both network- and user-centric for the uplink of cell-free wireless networks with centralized processing. Precisely, every user's reception involves a distinct subset of access points (APs) while every AP participates in the reception of a distinct subset of users, hence the moniker subset MMSE receivers. These subsets, defined on the basis of the large-scale channel gains between users and APs, capture the most relevant signal and interference contributions while disregarding those whose processing is cost-ineffective and whose associated channel estimations would incur unnecessary overheads. With that, subset reception approaches the performance of network-wide MMSE reception, offering a multiple-fold improvement over cellular and matched-filtering counterparts, while being scalable in terms of cost and channel estimation. Moreover, because the subsets overlap considerably, they can sometimes be advantageously combined and the computation of the corresponding receivers can share a hefty amount of processing.

In this paper, we consider the downlink power allocation problem where the objective is to maximize the sum-rate in software-defined radio access network (SDRAN). Using SDRAN, the power allocation is performed at a central controller with the channel state information (CSIs) received from the base stations (BSs). However, due to time variable nature of the fading channel and the control path delay between the controller and BSs, the central decisions at the controller might become outdated by the time each BS wants to transmit. Modeling channel fading by using a time-correlated channel model, the power allocation problem would consist of parameters which are random variables. In order to solve this problem, we use the stochastic optimization framework and propose two practical schemes. The first solution works in a completely centralized manner while the second one is performed collaboratively in the controller and BSs. We analyze these schemes for cellular networks with arbitrary number of BSs and present procedures to find the optimum power allocations. Finally, using different numerical experiments, we evaluate the performance of our proposed schemes. Significant improvement in comparison to the scenario without considering CSI variation is observed.

Authentication and tampering detection of the digital signals is one of the main applications of the digital watermarking. Recently, watermarking algorithms for digital images are developed to not only detect the image tampering, but also to recover the lost content to some extent. In this paper, a new watermarking scheme is introduced to generate digital self-embedding speech signals enjoying the self-recovery feature. For this purpose, the compressed version of the speech signal generated by a speech codec and protected against the tampering by the proper channel coding is embedded into the original speech signal. Experimental results show that the self-embedding speech signal is recoverable with proper speech quality for high tampering rates, without significant loss in the quality of the original speech signal.

Energy harvesting (EH) has emerged as a promising technique for Green Communications and it is a novel technique to prolong the lifetime of the wireless networks with replenishable nodes. In this study, the authors consider the energy shortage analysis of fixed rate transmission in communication systems with EH nodes. First, the authors study the finite‐horizon transmission and provide the general formula for the energy shortage probability (ESP). The authors also give some examples as benchmarks. Then, the authors continue to derive a closed‐form expression for infinite‐horizon transmission, which is a lower bound for the ESP of any finite‐horizon transmission. These results are proposed for both Additive White Gaussian Noise (AWGN) and fading channels. Moreover, the authors show that even under random energy arrival , one can transmit at a fixed rate equal to capacity in the AWGN channels with negligible aggregate shortage time. The authors achieve this result using our practical transmission schemes, proposed for finite‐horizon. Also, comprehensive numerical simulations are performed in AWGN and fading channels with no Channel State Information (CSI) available at the transmitter, which corroborate our theoretical findings. Furthermore, the authors improve the performance of our transmission schemes in the fading channel with no CSI at the transmitter by optimising the transmission initiation threshold.

The number of orthogonal frequency division multiplexing (OFDM) sub‐carriers in modern wireless communication systems such as Third Generation Partnership Project (3GPP) long term evolution (LTE) can be as high as 2048. Channel matrix of data sub‐carriers in conventional multiple‐input–multiple‐output (MIMO) receivers is derived by interpolating channel matrix of pilot sub‐carriers and MIMO detection is performed on each interpolated channel matrix. Symbol detection on sub‐carrier by sub‐carrier basis demands a very high computational power. This study presents the first very‐large scale integration implementation of a novel 4 × 4 interpolation‐based soft output minimum‐mean‐squared error (MMSE) MIMO detector which combines channel estimation and MIMO detection. The detector computes MMSE matrix on pilot sub‐carriers using proposed division‐free matrix inversion algorithm and obtains MMSE matrix of data sub‐carriers by interpolation, reducing computational complexity by more than 66%. The throughput of the implemented detector on Virtex‐7 field programmable gate array (FPGA) exceeds 1 Gbps with 2.1 µs latency.

It has been shown that for multi-carrier signals with \n subcarriers, the peak-to-mean envelope power ratio (PMEPR) of a random codeword generated from a symmetric spherical, QAM or PSK constellation is \log(n) asymptotically. Motivated by this result, recently a coding scheme with a rate of 1-\log_q(2) over a symmetric q-ary constellation has been proposed that achieves a PMEPR less than c \log(n), where c is a constant. The idea of this coding scheme is to adjust the sign of subcarriers using so-called Chernoff bound-based derandomization algorithm. In this paper, using Chernoff bound and second order exponential Markov bound in conjunction with Gaussian approximation, two new variations of the derandomization algorithm are presented that yield roughly the same statistical PMEPR at the same rate. Moreover, it is rigorously established that the asymptotic PMEPR of both these algorithms is exactly the same as that of the original derandomization algorithm. Given a fixed amount of memory, our new algorithms can reduce the complexity up to one order, i.e. from \O(n^3) to \O(n^2). On the other hand, given a fixed computational complexity, our algorithms can reduce the required memory down to half.

In this paper, we derive two classes of upper bounds on the achievable peak-to-mean envelope power ratio (PMEPR) of multicarrier signals, using codes with rate 1-\log_q(2) over a symmetric q-ary constellation. These bounds, derived by applying moment and exponential Markov inequalities of different orders to the derandomization algorithm for subcarrier sign adjustment, prove the existence of classes of codes with good PMEPR and fixed rate loss. For instance, in a multicarrier system with n = 512 subcarriers, we show that there exists a code with rate loss \log_q(2) and PMEPR less than 11.95 dB, while the PMEPR of the uncoded system is 27.1 dB, i.e. an improvement of 15.15 dB.

Binary NRZ signaling over single ended or fully differential parallel wired channels is commonly used for chip-to-chip communications. This paper presents differential vector signaling as a generalized new class of signaling for parallel wired links. Differential vector signaling has many of the benefits inherent to differential signaling while maintaining high pin efficiency of single ended parallel links and offers an alternative solution for high speed chip-to-chip interconnections. The signaling is viewed as a multi-wire coded communication system. The encoding method and the maximum likelihood decoding algorithm are presented. Also a variant of this signaling which requires a reduced complexity receiver is proposed.

In this paper, a new technique for characterization of digital-to-analog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs least square estimation to characterize the DAC from dc to any target frequency. Characterization is performed using a random sequence with certain temporal and probabilistic characteristics suitable for intended operating conditions. The technique provides a linear estimation of the system and decomposes nonlinearity into higher-order harmonics and deterministic periodic noise. The technique can also be used to derive the impulse response of the converter, predict its operating bandwidth, and provide far more insight into its sources of distortion

Application of Discrete Multi-tone (DMT) signaling to high-speed backplane interconnects requires major modifications to the well-known analysis methods applied to wireline communication systems. Tight power budgets in backplane links impose severe constraints on DMT block size and use of channel shortening filters in the system. Consequently, maximum throughput is achieved in a DMT system that is (residual) interference limited and water-filling is not applicable in its original form. In this paper, the DMT system is cast as a Second Order Conic (SOQ problem with peak transmit power as the constraint and optimum integer bit-loading and power allocation are achieved through a novel incremental integer bit-loading algorithm. The convex framework is subsequently used to find "practical" upper bounds on the performance of multi-tone signaling over highspeed links. The results indicate that DMT has the potential to achieve 15-23 Gbps over typical backplane channels and system requirements in terms of FFT block size and prefix length are obtained.

In this paper, we propose an innovative channel coding scheme called accumulate-repeat-accumulate (ARA) codes. This class of codes can be viewed as serial turbo-like codes or as a subclass of low-density parity check (LDPC) codes, and they have a projected graph or protograph representation; this allows for high-speed iterative decoding implementation using belief propagation. An ARA code can be viewed as precoded repeat accumulate (RA) code with puncturing or as precoded irregular repeat accumulate (IRA) code, where simply an accumulator is chosen as the precoder. The amount of performance improvement due to the precoder will be called precoding gain. Using density evolution on their associated protographs, we find some rate-1/2 ARA codes, with a maximum variable node degree of 5 for which a minimum bit SNR as low as 0.08 dB from channel capacity threshold is achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA, IRA, or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore, by puncturing the inner accumulator, we can construct families of higher rate ARA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results are provided and compared with turbo codes. In addition to iterative decoding analysis, we analyzed the performance of ARA codes with maximum-likelihood (ML) decoding. By obtaining the weight distribution of these codes and through existing tightest bounds we have shown that the ML SNR threshold of ARA codes also approaches very closely to that of random codes. These codes have better interleaving gain than turbo codes

Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This paper proposes an approach that incorporates a baseband (BB) channel and a few passband (PB) channels. In this MT system inter- channel interference (ICI) and inter-symbol interference (ISI) are eliminated through fractionally spaced equalization at the transmitter and feedback equalization at the receiver. The design is modeled as a MIMO system, and optimal equalizer coefficients to minimize the transmit peak voltage are found by casting the optimization as a Second Order Conic (SOC) problem. In addition, for systems that need adaptation, we show how equalizer and power allocation coefficients can be obtained (sub optimally) using Zero Forcing (ZF) optimization. The effect of transmitter and receiver clock jitter are modeled in a way that can be included in both SOC and ZF optimizations, and the performance of this system is compared to more conventional baseband examples. It is shown that this AMT system can be built with complexity/power similar to a comparable performance baseband system, but has the ability to scale to higher bit rates.

We propose an innovative channel coding scheme called "accumulate repeat accumulate codes" (ARA). This class of codes can be viewed as serial turbo-like codes, or as a subclass of low density parity check (LDPC) codes, thus belief propagation can be used for iterative decoding of ARA codes on a graph. The structure of encoder for this class can be viewed as precoded repeat accumulate (RA) code or as precoded irregular repeat accumulate (IRA) code, where simply an accumulator is chosen as the precoder. Thus ARA codes have simple, and very fast encoder structure when they representing LDPC codes. Based on density evolution for LDPC codes through some examples for ARA codes, we show that for maximum variable node degree 5 a minimum bit SNR as low as 0.08 dB from channel capacity for rate 1/2 can be achieved as the block size goes to infinity. Thus based on fixed low maximum variable node degree, its threshold outperforms not only the RA and IRA codes but also the best known unstructured irregular LDPC codes with the same maximum node degree. Furthermore, by puncturing the accumulators, any desired high rate codes close to code rate 1 can be obtained with thresholds that stay close to the channel capacity thresholds uniformly. Iterative decoding simulation results are provided. The ARA codes also have projected graph or protograph representation, that allows for high speed decoder implementation.

Repeat-accumulate (RA) codes are the simplest turbo-like codes that achieve good performance. However, they cannot compete with turbo codes or low-density parity-check codes (LDPC) as far as performance is concerned. The accumulate-repeat-accumulate (ARA) codes, as a subclass of LDPC codes, are obtained by adding a pre-coder in front of the RA codes with puncturing, where an accumulator is chosen as the precoder. These codes not only are very simple, but also achieve excellent performance with iterative decoding. In this paper, the performance of these codes with maximum likelihood (ML) decoding are analyzed and compared to the random codes by very tight bounds. The weight distributions of some simple ARA codes are obtained, and through existing tightest bounds we have shown that the ML SNR thresholds of the ARA codes approach very closely to the performance of random codes. We have shown that the use of a precoder improves the SNR threshold but the interleaving gain remains unchanged with respect to the RA codes with puncturing.

An innovative channel coding scheme called "accumulate repeat accumulate codes" (ARA) is proposed. ARA codes can be viewed as a subclass of low density parity check (LDPC) codes with fast encoder, and they have a projected graph or protograph representation. Using density evolution on their associated protographs, we find examples of rate 1/2 ARA codes with maximum variable node degree 5 for which a minimum bit SNR as low as 0.08 dB from channel capacity can be achieved as the block size goes to infinity. A family of high rate ARA codes with thresholds that stay uniformly close to their respective channel capacity thresholds are constructed. The ensemble weight distribution and ML threshold for rate 1/2 ARA codes were computed. For ARA with repeat 4, the ML threshold approaches within 0.005 dB of the ML threshold of random codes based on the existing tightest closed form bound.

Recently some efficient parallel architectures for turbo decoder have been proposed. In these architectures the bottleneck for the parallelization of the decoder is the interleaver. On the other hand, turbo codes achieve a very impressive near Shannon-capacity performance in which the interleaver plays a crucial role. Therefore, it is of great interest to design interleaves that are good from both performance and parallelization point of views. In this paper we propose an interleaver structure that is very suitable for parallelization of turbo decoders. It is shown that such an interleaver can be designed to have good BER performance as well. By this structure not only fast decoders with very low latency can be built, but also the regularity of the decoder and the simplicity of the interleaver structure make them very promising for VLSI implementation. We also present a fast algorithm to design such an interleaver, which can be used to design S-random interleavers as well. Such interleavers have been designed and the performances are compared to that of S-random interleavers by simulations.

Interleavers play a critical role in the performance of turbo codes. They can be best designed given the structure of the code. In this paper a new methodology for systematically designing the interleaver for a parallel-concatenated convolutional code (PCCC) is presented that exploits the structure of the code. Some novel approaches that result from this methodology are introduced. This methodology can be a basis for constructing algorithms to design very good interleavers for turbo-like codes. This algorithm tries to maximize the minimum distance of the code. The performance of the interleavers designed with this methodology is compared with previous methods and its superiority is illustrated by simulation results.

Turbo codes not only achieve near Shannon-capacity performance, but also have decoders with modest complexity, which is crucial for implementation. So far efficient architectures for decoding of turbo codes have been proposed that are suitable for sequential processing. In this paper a novel parallel processing architecture for a very high-speed turbo decoder is presented. The performance of this decoder and the tradeoff between speed and efficiency are discussed. It is shown that some decoders can run faster by some orders of magnitude while maintaining almost the same processing load. A systolic implementation of this decoder is presented at the end.