Demo Data from VLDB 2026 / reviewers in the wild / expert
Hongcheng Xu
dblp:35/10181
· DBLP profile ↗
6ranked-venue papers
4as first author
2since 2021 · last 2023
0000-0002-2813-3230ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 3 first-author · 1 since 2021Computer networks · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 70% Performance modeling and evaluation · 23% Parallel and multicore computing · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › lithography
electron beam lithography |
0.7 | 1 | 2023 | Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Performance modeling and evaluation › numerical algorithms
fast multipole method |
0.7 | 1 | 2023 | Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation › physical design
lithography |
0.7 | 1 | 2023 | Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation › physical design
optical proximity correction |
0.7 | 1 | 2023 | Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Parallel and multicore computing
parallel computing |
0.2 | 1 | 2023 | Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Methods — techniques the papers use, named apart from their topics
fast multipole method · 0.72D-FFT · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam LithographyabstractIn electron beam lithography (EBL), the proximity effect seriously influences pattern resolution under high-precision conditions. Mainstream proximity effect correction (PEC) methods based on 2-D fast Fourier transform (2D-FFT) calculate a large number of unexposed points; thus, it may suffer from low efficiency especially when the exposure layout is unevenly distributed. This article proposes an efficient unequally spaced grid PEC method for EBL based on the fast multipole method (FMM). FMM in PEC just calculates the interaction between all the exposure points, and thus, it gets rid of the limitation of the equally spaced grid. Compared to the state-of-the-art PEC method based on 2D-FFT, the calculation speed of FMM will exceed the current fastest 2D-FFT convolution when the layout exposure density is below a certain proportion (approximately 80% under the 10-thread CPU parallel computing conditions). For the application of integrated circuit (IC) mask industry, the error of FMM is within the acceptable range of PEC. The PEC method in this article has been applied to a free software via software as a service (SaaS) mode, and a Windows-based EBL simulation and optimization software toolkit “HNU-EBL,” which is freely available athttp://www.ebeam.com.cn. Wenze Yao, Haojie Zhao, Chengyang Hou, Hongcheng Xu, Xin Zhang 0055 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 2022 | Flexible Gas-Permeable and Resilient Bowtie Antenna for Tensile Strain and Temperature SensingabstractAs a wireless basic unit, flexible antennas hold a wide range of applications in wearable electronics, soft robotics, and Internet of Things (IoT). However, most of the current flexible antennas are encapsulated by silicone elastomers with poor gas permeability, which severely hinders the evaporation of skin moisture and sweat. In addition, conventional rigid metals as high-frequency conductors are limited by poor elasticity and susceptibility to oxidation for on-skin application. Here, we developed a highly permeable and stretch-resistant flexible bowtie antenna that can capture changes in tensile strain and temperature. A low-impedance flexible carbon nanotube-silver (CNT-Ag) substrate was fabricated as the conductor of the antenna. By optimizing the multibeam bowed geometry and wrapping it in porous thermoplastic polyurethane (TPU) fibers, the final five-beam antenna was obtained and was able to withstand a relatively large tensile stress of 25.2 MPa, yet achieve a high vapor transmission rate of 48.2 mg cm−2 h−1. The antenna obtained an ideal impedance match at 2.28 GHz with doughnut-like radiation and a high radiation efficiency of over 85%. Furthermore, the antenna was successfully used to capture the strain in the wrist epidermis during bending and to detect thermal changes in the beaker of hot water, respectively. Finally, demonstrations of the antenna, such as permeability, radiation to the human body, and integrality in connection with flexible circuits, were carefully developed to reveal its feasibility in the real world. We expect this work to pave the way for the future establishment of epidermally flexible antennas for soft electronics. Hongcheng Xu, Weihao Zheng, Yangbo Yuan, Dandan Xu, Yuxin Qin, Ningjuan Zhao, Qikai Duan, Yujian Jin, Yuejiao Wang, Yang Lu 0002, Libo Gao |
IEEE Internet Things J. | 1 |
| 2014 | Wide-band efficiency-enhanced CMOS rectifierabstractWe present in this paper the design of a wide-band efficiency-enhanced CMOS rectifier. A novel semi-active diode is proposed to minimize both the diode forward voltage drop and the reverse leakage current. This is achieved by dynamically configuring the rectification device as a threshold compensated diode in the on-state while a standard MOS diode in the offstate, respectively. The proposed rectifier is implemented in a 0.35μm 4M/2P standard CMOS process. In simulation, with 5.5V AC input at 13.56MHz, the rectifier outputs 4.94V DC voltage across a 1.2kΩ load resistor, achieving 87% power conversion efficiency (PCE) and 90% voltage conversion efficiency (VCE). The PCE and VCE can be maintained from 1MHz to 20MHz input frequency, with only 3% deviation in the PCE and 2% deviation in the VCE. In addition, the performance of the rectifier is self-compensated over temperature and process. From -40°C to +130°C, the simulated VCE varies within 2% from 89.6% to 87.7%, while the PCE stays almost constant at 86%. With 200 Monte Carlo samples, the standard deviation in the PCE and VCE are as low as 0.56% and 0.57%, respectively. Hongcheng Xu, Matthias Lorenz, Ulrich Bihr, Jens Anders, Maurits Ortmanns |
ISCAS | 1 |
| 2013 | A bidirectional neural interface with a HV stimulator and a LV neural amplifierabstractThis paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology. Ulrich Bihr, Thomas Ungru, Hongcheng Xu, Jens Anders, Joachim Becker, Maurits Ortmanns |
ISCAS | 3 |
| 2013 | A multi-channel neural stimulator with resonance compensated inductive receiver and closed-loop smart power managementabstractThis paper presents an integrated neural stimulator with highly efficient power management solution, which is intended for a 1024 channel epi-retinal implant. The stimulator features an adaptive high quality LC matching network that compensates for the process variation in the resonance frequency of the inductive receiver and maximizes the link power transmission efficiency. Transcutaneous closed-loop power control is realized that enables optimum power transfer in spite of the coupling variation as well as the variation in the stimulation threshold/current. Finally, a programmable adaptive supply in the high voltage (HV) domain is implemented so to minimize the power dissipation during the active stimulation mode in terms of stimulus current/electrode impedance inconsistencies. The stimulator prototype is designed in AMS 0.35μm HV CMOS technology. In simulation, the power transmission efficiency of the telemetric link is improved by a factor of 2 by the resonance compensation circuits. In addition, automatic supply voltage adaptation of the stimulator from 13.1V to 8V has been achieved, resulting in maximum power saving of 40% for the implantable circuit. Hongcheng Xu, Ulrich Bihr, Joachim Becker, Maurits Ortmanns |
ISCAS | 1 |
| 2012 | A new class of integrated CMOS rectifiers with improved PVT-compensated efficiencyabstractWe review in this paper a new class of integrated CMOS rectifiers with improved PVT-compensated efficiency and propose also a new voltage quadrupler. By utilizing a threshold compensation technique, the presented circuits are able to achieve both high voltage conversion efficiency (VCE) and power conversion efficiency (PCE) with only standard threshold devices at low input amplitudes. Besides, the performance of the rectifiers is selfcompensated over process and temperature, which is achieved by precisely tracking the diode threshold drift with an auxiliary dummy. The rectifiers are implemented in AMS 0.35μm 4M/2P standard CMOS process and the simulated performance is shown at an input frequency of 13.56MHz. For the proposed voltage quadrupler, at 0.8V input amplitude and 2kΩ load resistor, output voltage of 1.52V can be achieved with VCE and PCE of 48% and 49%, respectively. As compared to previously published results, the improvement is up to 358% in VCE and 351% in PCE. Besides, the maximum deviation in its output voltage is as low as 162mV over 100°C temperature span, which outperforms the conventional structure by almost an order of magnitude. Hongcheng Xu, Maurits Ortmanns |
ISCAS | 1 |