The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

Ferroelectric memory devices have emerged as a promising class of non-volatile memory technologies, offering a unique combination of high-speed operation, low power consumption, and good endurance compared to conventional flash memory. These devices leverage the bistable polarization states of ferroelectric materials to store data, enabling nonvolatile retention while maintaining fast read/write capabilities. The discovery of hafnium-based ferroelectric materials that are fully CMOS compatible and exhibit robust ferroelectricity at nanoscale dimensions has further enhanced their integration and scalability potential. For IoT devices, which require non-volatile state retention under constrained power budgets and frequent interruptions, we propose a novel FeAND memory cell designed to serve as a non-volatile backup for volatile memory. Unlike conventional ferroelectric memories that rely on current sensing, our design directly outputs a voltage signal, eliminating the need for sensing circuits. The cell exhibits a logical AND-like behavior, enabled by an innovative read scheme based on a CMOS inverter. The cell can function as both a non-volatile memory element and a logic gate where one input is permanently stored as a polarization state. This dual functionality enables novel Computing-in-Memory architectures by embedding logic operations directly within the memory array. We validate our design using Cadence Spectre simulations with the GlobalFoundries 28SLP technology.

The promising features introduced by the integration of ferroelectric devices into conventional integrated circuit fabrication processes have spurred extensive research into device reliability, non-volatile memory circuits and system-level applicability. Their low-power operation makes them particularly suitable for Internet of Things applications, and their intrinsic memory properties position them as strong candidates for nonvolatile memory technologies and In-memory Computing. For such data-intensive applications, the need to ensure secure data storage, processing and transmission has motivated the adaptation of classic hardware security strategies to this emerging inmemory computing paradigm, demonstrating high effectiveness with ferroelectric designs. However, a variability analysis from a design perspective remains unexplored towards either implementing security primitives based on identity, e.g. Physical Unclonable Functions, or based on stochasticity, e.g. True Random Number Generators.In this work, we focus on the variations expected in a commercial 28 nm process and its compatibility with memory cell design, in view of the implementation of a Physical Unclonable Function in a ferroelectric memory array. In particular we show that while obtaining a sufficient output variability, which can be used for fingerprinting the device, a fair current ratio is maintained, allowing memory array implementations.

Non-volatile in-memory computing (iMC) has emerged as an energy-efficient paradigm well suited to AI workloads. Its implementation using 1T1C FeMFETs (Ferroelectric Memory Field Effect Transistors), a best-in-class emerging nonvolatile memory technology that integrates BEOL ferroelectric devices with FEOL transistors, is of particular interest. This interest stems from their potential to enable large-scale multiplyaccumulate (MAC) operations in both digital and analog domains. However, realizing tangible performance benefits requires comprehensive cross-layer exploration of both design and technology parameters, extending up to accelerator level. In this work, we propose a bitcell-level multi-objective optimization methodology to identify and extract optimal sizing solutions that provide tractable trade-offs between key performance indicators (KPI). We further demonstrate how this approach facilitates cross-stack exploration of accelerator architectures. Results are presented as Pareto fronts spanning $2-4 \mathrm{KPIs}$: a $2-\mathrm{KPI}$ problem illustrates the methodology, while a $\mathbf{4}$-KPI problem represents a realistic design scenario. Comparison is made between $\mathbf{1 3 0} \mathbf{n m}$ and 28 nm technologies demonstrating a decrease in the average of write energy and area up to 24 X and 30 X respectively.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube$(N^{2}C^{2})$, which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

The vertical nanowire field effect transistor (VN-WFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, such a technology enables designs with improved energy-efficiency as well as reduced footprint and thus interconnect capacitance. In this work, and based on the compact model of a real VNWFET device, we present the design flow for the generation of a standard cell library starting from the circuit and physical design of logic cells to logic synthesis based on the VNWFET technology. The results on the synthesized benchmark cells, as compared against 45nm and 65nm CMOS libraries, demonstrate a significant decrease in the average dynamic power consumption and delay values up to 71X and 34X respectively, with anaveragearea gain of up to 5X. However, an increase in leakage power consumption (up to 2X on average) was also observed.