Self-Supervised Learning (SSL) has shown great promise in learning representations from unlabeled data, making it widely used in real-world applications. However, SSL methods have been shown to be vulnerable to backdoor attacks, where adversaries manipulate representations by tampering with training data or the model. This work focuses on defending against backdoor attacks in SSL, assuming the adversary has partial access to training data but no access to the model. We propose computationally efficient and generalizable methods for SSL robustness using two frequency domain augmentations: Gaussian Blur and Frequency Patching. Our method mitigates backdoor attack success by 60-80% while increasing performance by 5-8% on downstream classification tasks. We also demonstrate increased adversarial robustness using the RobustBench framework. Code for our work is available at https://github.com/Aryan-Satpathy/Backdoor.

In this paper, we have proposed a negative capacitance (NC) L shaped channel tunnel field-effect transistor (NC-LTFET), which consists of a hafnium oxide$(\text{HfO}_{2})$based ferroelectric (FE) layer in the gate stack. The presence of polarization phenomena in the FE layer tends to enhance the internal voltage and electric field, which result higher ON-state current and steeper subthreshold swing (SS). From well calibrated 2-D TCAD simulation results, it is revealed that the NC-LTFET outperforms the conventional LTFET in terms of both static and dynamic energy dissipation. The NC-LTFET exhibits$\sim 430 \times$and$\sim 10^{4} \times$higher ON-state current and$I_{O N} / I_{O F F}$ratio, respectively, as compared to the conventional LTFET. In addition, the proposed NC-LTFET shows$\sim 2.2 \times, \sim 10^{2} \times$and$\{\sim} 10^{2} \times$low SS, switching delay and energy delay product (EDP), respectively as compared to the conventional LTFET. As a result, NC-LTFET is$10 \times$higher energy efficient for both memory and logic designs switching at ultra-low supply voltage$(<0.2 ~\mathrm{V})$when compared to the conventional MOSFET and LTFET.

The Advanced Peripheral Bus (APB4) protocol, a component of the AMBA 4 specification, is designed to connect low-bandwidth peripherals to high-performance system-on-chip (SoC) designs. This paper presents the design, implementation, and verification of the APB4 protocol using Verilog HDL and SystemVerilog-based Universal Verification Methodology (UVM). We extend the standard APB4 protocol by incorporating power gating techniques and burst-mode support to enhance power efficiency and throughput. Simulation and synthesis were performed using Xilinx Vivado and Synopsys VCS, with verification data showing 100% functional coverage and zero protocol violations. Simulation results using ModelSim and Synopsys VCS confirm accurate protocol behavior, while synthesis using Xilinx Vivado and power analysis via XPower Analyzer demonstrate a 66% reduction in dynamic power and 7% area optimization compared to prior APB implementations. This work positions the APB4 protocol as a viable low-power solution for energy-constrained SoC designs, providing a reusable and modular verification infrastructure aligned with modern digital design flows.

Stress-strength reliability is widely used in manufacturing industry for producing good quality equipment. A new stress-strength index has been introduced when strengths of$k$independent components follow exponential distributions with different scale parameters. We obtain the maximum likelihood estimator, a uniformly minimum variance unbiased estimator, a Bayes estimator, and an analogue of the best scale equivariant estimator for the new index. It is shown that the Bayes estimators' limit is a generalized Bayes estimator under the squared error loss function. The asymptotic distribution of the MLE is derived using the multivariate delta method. A detailed comparison of the risk performance of all these estimators is done numerically. The results are illustrated by two real data analyses.

There are various situations where prior information is available on parameters in the form of order relations. One needs to take into account this information to obtain superior estimators. Shannon modeled uncertainty mathematically and called it entropy. In this paper, we study the problem of estimating entropy of two exponential populations associated with a common scale parameter, and unknown but ordered location parameters. In particular, the unrestricted best affine equivariant estimator is shown to be inadmissible under order restricted location parameters with respect to a class of location invariant loss functions. Under some specific location invariant loss functions, various improved estimators are obtained. Applications of this problem are developed for various sampling schemes: (i) i.i.d. sampling, (ii) record values, (iii) Type-II censoring and (iv) progressive Type-II censoring. Numerically, we have compared the risk performance of the proposed estimators for the squared error and linex loss functions.

In this work, the performance of feedforward neural network with a descent gradient of distributed error and the genetic algorithm (GA) is evaluated for the recognition of handwritten ‘SWARS’ of Hindi curve script. The performance index for the feedforward multilayer neural networks is considered here with distributed instantaneous unknown error i.e. different error for different layers. The objective of the GA is to make the search process more efficient to determine the optimal weight vectors from the population. The GA is applied with the distributed error. The fitness function of the GA is considered as the mean of square distributed error that is different for each layer. Hence the convergence is obtained only when the minimum of different errors is determined. It has been analysed that the proposed method of a descent gradient of distributed error with the GA known as hybrid distributed evolutionary technique for the multilayer feed forward neural performs better in terms of accuracy, epochs and the number of optimal solutions for the given training and test pattern sets of the pattern recognition problem.