Precision timing is a fundamental requirement for ultralow-power Internet-of-Things (IoT) nodes, wildlife trackers, and wearable health devices. However, maintaining accuracy in these severely power-constrained systems is difficult due to the mechanical shock sensitivity of crystal oscillators (XOs). This work proposes a ratio wake-up timer (Ratio-WUT) designed to enhance XO shock resilience with very low power overhead. The system integrates a 5.58 nW XO with a secondary ultralow-power auxiliary oscillator (AuxO). A 1.75 nW digital controller actively monitors the ratio between XO and AuxO cycles, triggering an autonomous restart sequence immediately upon detecting an XO failure. Unlike conventional hybrid timers that rely on periodic wake-up checks, the Ratio-WUT provides continuous, real-time fault detection and correction. The prototype features a custom 180 nm CMOS XO and subthreshold AuxO, with control logic validated on an FPGA. Detailed postlayout analysis of a fully integrated version estimates a total power consumption of 7.33 nW. Experimental validation confirms the system’s ability to recover from mechanical shock events in real-time while maintaining wake-up functionality. By leveraging the inherent stability of the XO for timing while using the AuxO for supervision, the Ratio-WUT achieves a$3.85\times $power reduction compared to prior hybrid architectures.

This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.

Advanced Internet-of-Things (IoT) devices are increasingly used in high-temperature environments, such as automotive, aerospace, defense, and industrial applications. High-temperature voltage references are crucial for these systems. This paper presents two topologies designed for high-temperature operation. The first topology minimizes design costs by using a replica branch to decouple leakage from the core, reducing its impact on the reference voltage. The second topology optimizes the operating temperature by employing one-stage amplifiers as buffers to handle junction leakage while maintaining body voltage. Both designs are fabricated in a 180 nm CMOS process. The first design supports operation up to 140∘C with an average temperature coefficient (TC) of 70 ppm/∘C, while the second design operates up to 170∘C with a TC of 64 ppm/∘C. The designs also exhibit line sensitivities of 0.46 %/V and 0.31 %/V, PSRRs of –37.8 dB and –38.3 dB at 100 Hz, and power consumption of 111 pW and 136.8 pW at room temperature, respectively.

Achieving precise timing in miniature systems attached to monarch butterflies is challenging due to the shock sensitivity of crystal oscillators (XOs) and the limited accuracy ofRCoscillators. This brief proposes a hybrid timestamping technique that combines both oscillators as timers to deliver shock-resistant, high-accuracy timing. Three algorithms are evaluated to fine-tune a multiplier (M), the ratio of the two timers’ speeds, for improved responsiveness and robustness against temperature and voltage variations. The direct ratioing algorithm proves the most effective, determining the correctMwithin a single wake-up cycle and reducing time shift error by 145 times in a 12-h test, compared to using anRCtimer alone. This work leverages the existing hardware and introduces new firmware, easily implementable using standard digital circuit design flows, to significantly enhance timing precision and shock resilience in millimeter-scale butterfly tracking systems, making a valuable contribution to the VLSI community.

An accurate wake-up timer is crucial for low-power wireless Internet-of-Things (IoT) devices. Although duty cycling minimizes power consumption, synchronization with a base station or other devices requires periodic activation. Inaccuracies in the wake-up timer extend the active duration around the expected synchronization time, leading to increased energy consumption, which is especially critical in high-duty-cycle operations. This article presents a low-power digital compensation method to enhance the accuracy of a crystal oscillator (XO)-based wake-up timer over varying temperatures. The proposed approach dynamically adjusts the digital counter threshold value at each wake-up to compensate for XO frequency shifts caused by temperature changes. Delta-sigma ($\Delta \Sigma $) modulation further reduces quantization noise for fractional time corrections. This work demonstrates the proposed technique on an existing low-power, miniature IoT system incorporating an exponential temperature sensor and employs two key strategies: 1) approximating the compensation curve as linear segments for simpler calculations and 2) replacing division-heavy operations with a successive approximation (SAR) method. These methods reduce the system’s time-shift error from 64.7 to 3.6 ppm using a single-point room-temperature calibration combined with adaptive temperature compensation, with a power overhead of only 7.92% (8.22 nW compensation +5.58 nW XO). Furthermore, a custom digital circuit for compensation minimizes the system power overhead to 5.07% (3.24 nW compensation +5.58 nW XO). Compared to state-of-the-art temperature-compensated XOs (TCXOs) using analog approaches, the proposed design reduces the power consumption by a factor of$2.37\times $while meeting the required time-error specification.

We propose a low-power voltage reference that enables independent adjustment of temperature sensitivity and output level. This design enhances the temperature sensitivity without impacting the output level distribution, in contrast to previous methods. The proposed circuit achieves this by integrating a separate control system that utilizes diode-connected pMOS transistors and an analog multiplexer for output level adjustment, along with biasing current control to improve the temperature sensitivity. In a 180-nm CMOS process, the prototype circuit generates a stable reference voltage averaging 192 mV, maintaining an accuracy of ±8.8 mV ($\pm 3\sigma $) from 0 °C to 75 °C across ten samples. In addition, it consumes only 35.8 pW at 0.6 V and 25 °C.

This brief introduces a compact-size hardware accelerator for dynamic neural fields (DNF) used in object tracking. To address the substantial computational workload and memory occupancy associated with conventional DNFs, three key approaches are implemented: kernel size reduction and abstraction, the replacement of sigmoidal functions with comparison operations, and the approximation of rectangular-shaped objects. The design is realized in a 28-nm CMOS process, resulting in a layout with an area of 0.53 mm2. Simulation results demonstrate that the accelerator processes$256 \times 256$dynamic vision sensor (DVS) frames at 211 frames per second (fps), with a power consumption of 1.68 mW under such conditions.

This paper proposes a switched-capacitor network (SCN) based fractional bandgap voltage reference (BGR) circuit designed in 180nm CMOS process to achieve high accuracy and low power consumption for implantable biomedical applications. The design proposes a$V_{EB}$generator that employs a 2x charge pump and an improved SCN to generate a temperature inde-pendent reference voltage$(V_{REF})$’. A low-power clock generator circuit is proposed, which reduces the leakage current by 37 % compared to previous works, thereby reducing the circuit's power consumption to 18.5nW at typical conditions. The design works from a supply voltage of 0.5V and has a TC of 74. Sppm/${}^{\circ} \mathrm{C}$over a temperature range of$0-80^{\circ} \mathrm{C}$. The PSRR of the circuit is -62.9dB at 100Hz. Based on the Monte Carlo simulations of 500 samples, we obtain an untrimmed$3\sigma/\mu$of 2.6%. The design occupies an active area of 0.027mm2.

This paper proposes a 162nW resistance-to-digital converter (RDC) for miniature battery-powered sensing systems. The RDC first converts input resistance to a pulse by charging a capacitor to a threshold voltage with a current proportional to the resistance. It compensates temperature sensitivity of the charging current by generating the threshold voltage with the same temperature dependency. Then, the circuit digitizes the pulse using an up-down counter that cancels temperature-dependent delay and offset of the low-power comparator in a digital Correlated Double Sampling (CDS) style. Designed in a 180 nm CMOS process, the proposed circuit achieves a figure-of-merit (FoM) of 0.845pJ/c.s. in simulation, with a conversion time of 50 ms for input resistance from$50\mathrm{k}\Omega$to$1\mathrm{M}\Omega$, while consuming 162nW at a supply voltage of 900 mV. Also, it obtains a temperature sensitivity of 26.9ppm/°C from −40 to 100°C. Compared with the state-of-the-art RDCs, this work improves the FoM and temperature sensitivity by 42.91% and 11.52%, respectively.

This paper proposes a low-power relaxation oscillator for low-power high-temperature IoT systems. It generates a 959 Hz clock signal from −40 to 170°C, consuming 6.75 nW at 0.65 V. A proposed switch-leakage compensation scheme nullifies the effects of body diode and subthreshold leakages on oscillator output frequency at high temperatures, thereby obtaining a wide operating temperature range. The oscillator implemented in a 180 nm CMOS process achieves a temperature coefficient of 40 ppm/°C from −40 to 170 °C at 0.65 V and a line sensitivity of 0.5 %/V from 0.65 to 2.4 V at room temperature, in simulation. Compared with state-of-the-art sub-$\mu\mathrm{W}$oscillators, this circuit obtains the highest operating temperature and the maximum temperature range.

The paper presents a 0.5V supply, gate leakage-based current/voltage reference for ultra-low power IoT and biomedical applications. The references are generated by the proper addition of PTAT and CTAT curves, which are obtained by exploiting the traditional architecture of the beta multiplier and using the body biasing effect. Gate leakage transistors replace the resistors to ensure low power and low area. The circuit doesn't involve any Op-Amps avoiding the issues of offset that are prominent in these circuits. Implemented in CMOS 90nm technology, the proposed current (voltage) reference achieves a typical accuracy of$34.6\text{ppm} /{ }^{\circ} \mathrm{C}(29.68 \text{ppm} /{ }^{\circ} \mathrm{C})$over a wide temperature range of$-55^{\circ} \mathrm{C}$to$75^{\circ}\mathrm{C}$with typical value 63.32pA(0.35V). Excellent line sensitivity of 0.0318%N and 0.0576%N are observed for voltage and current reference, respectively, in a supply range of 0.5V - 2.3V. The area occupied by the total circuit is 0.0096mm2, while the power consumption is 415pW at the typical corner of$27^{\circ}C$and 0.5V supply.

This brief presents an energy-efficient accelerator for convolutional neural network (CNN) layer computations in a compact system. The accelerator replaces traditional data shift registers with a multiplexer-based barrel shifter, offering greater flexibility for supporting various models and reducing power consumption by 56.2% compared to flip-flop-based shifters. The prototype, fabricated using a 180-nm CMOS process, accelerates CIFAR-10 dataset CNN computations by 8.5 times compared to a system without the accelerator. It achieves this speedup while consuming only$4.7 ~\mu \text{W}$of power and$9.53 ~\mu \text{J}$for each inference task.

We propose a low-power voltage reference of which temperature coefficient (TC) and absolute output level are independently adjustable. It enables to optimize TC without sacrificing output level distribution, compared with the previous works. The design provides the separate control by employing a DAC using diode-connected PFETs and an analog multiplexer for the output level trimming, in addition to biasing current control for TC improvement. Fabricated in a 180 nm CMOS process, the proposed circuit generates a stable reference voltage of 192 mV on average, with a $\pm 3 \sigma$ inaccuracy of 8.8 mV from 0 to $75^{o}\mathrm{C}(10$ samples), while consuming only 35.8 pW at 0.6 V and $25^{o}\mathrm{C}$.

The paper presents a sub-nW gate-leakage based voltage and current reference in a single circuit whose reference values are scalable and doesn’t incorporate start-up circuits or resistors in the architecture. The power consumption of the proposed circuit increases by only 2.1x in the temperature range of -55°C to 100°C, unlike conventional voltage/current references where the power consumption increases exponentially w.r.t temperature. Implemented in 90nm technology, the proposed voltage reference (current reference) achieves post-trim typical accuracy of 22ppm/°C(58ppm/°C) and worst-case accuracy of 71ppm/°C(78ppm/°C). Excellent line sensitivities of 0.029%/V and 0.059%/V are observed for voltage and current reference respectively, in a supply range of 1V - 3V. Without any start-up circuit, the observed 99% settling times for voltage and current reference are 1.92ms and 2.526ms respectively. The area occupied by the total circuit is 0.0015mm2, while the power consumption is 156pW at typical corner, 27°C and 1V supply.

Implementing a neural network (NN) inference in a millimeter-scale system is challenging due to limited energy and storage size. This article proposes an energy-aware adaptive NN inference implementation that utilizes one of two exits with different accuracies and computation options. The early-exit path provides a shorter processing time but less accuracy than the main-exit path. To compensate for the reduced accuracy, it additionally applies the main-exit path if the entropy of the early-exit inference is higher than a predetermined value. The NN is implemented with a custom low-power 180-nm CMOS processor chip and a 90-nm embedded flash memory chip and tested by the CIFAR-10 dataset. The measurement results show that the implemented convolutional NN (CNN) reduces processing time and thus energy consumption by 43.9% compared with a main-exit-only method while sacrificing its accuracy from 69.9% to 66.2%. Also, we explore the required minimum battery capacity at each optimal configuration for accuracy and/or energy consumption to achieve energy-autonomous operation under measured exemplary light profiles. It requires a minimum battery capacity of 855 mJ, acceptable for the target miniature system with two millimeter-scale batteries (684 mJ each). Compared with the state-of-the-art CNN technique (BranchyNet) allowing early stopping, the proposed design improves the accuracy by 0.7% and 3.3% to maintain energy-autonomous operation with two and one millimeter-scale batteries, respectively. Compared with the state-of-the-art lightweight CNN technique (MobileNet), this work provides flexibility with a tradeoff between accuracy and processing time for different application requirements.

This paper describes a miniature edge device that performs neural network inference with different exit options depending on available energy. In addition to the main-exit path, it provides an alternative, early-exit path that requires less computation and thus increase the number of inference operations for given energy. To compensate its degraded accuracy, the proposed device provides entropy as a confidence level for the early exit. The network is implemented with a custom low-power 180 nm CMOS processor chip and a 90 nm embedded flash memory chip and tested by images from CIFAR-10 dataset. The measurement results show the proposed neural network reduces processing time and thus energy consumption by 41.3% compared with the main-exit only method while sacrificing its accuracy from 69.5% to 66.0%.

Each fall, millions of monarch butterflies across the northern US and Canada migrate up to 4,000 km to overwinter in the exact same cluster of mountain peaks in central Mexico. To track monarchs precisely and study their navigation, a monarch tracker must obtain daily localization of the butterfly as it progresses on its 3-month journey. And, the tracker must perform this task while having a weight in the tens of milligram (mg) and measuring a few millimeters (mm) in size to avoid interfering with monarch's flight. This paper proposes mSAIL, 8 × 8 × 2.6 mm and 62 mg embedded system for monarch migration tracking, constructed using 8 prior custom-designed ICs providing solar energy harvesting, an ultra-low power processor, light/temperature sensors, power management, and a wireless transceiver, all integrated and 3D stacked on a micro PCB with an 8 × 8 mm printed antenna. The proposed system is designed to record and compress light and temperature data during the migration path while harvesting solar energy for energy autonomy, and wirelessly transmit the data at the overwintering site in Mexico, from which the daily location of the butterfly can be estimated using a deep learning-based localization algorithm. A 2-day trial experiment of mSAIL attached on a live butterfly in an outdoor botanical garden demonstrates the feasibility of individual butterfly localization and tracking.

An ARM-based sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. The ultra-low power chip featuring an ARM Cortex-M0 processor, 3kB of SRAM, and power management unit (PMU) with energy harvesting from MFCs is designed to consume 11nW in sleep mode for perpetual sensing operation. A small-scale micro-MFC with 21.3cm2anode surface area was connected to the on-chip PMU to charge a thin film battery of 1mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1 sec wake-up time demonstrated the sustainability of chip-on-mud concept. During sleep mode, the system charges the 4V battery at 380nA from the micro-MFC generating 5.4μW of power, which can support up to 20mA of active mode current.

This paper proposes an energy-efficient VGA full-frame feature extraction processor design. It is based on the SURF algorithm and makes various algorithmic modifications to improve efficiency and reduce hardware overhead while maintaining extraction performance. Low clock frequency and deep parallelism derived from a one-sample-per-cycle matched-throughput architecture provide significantly larger room for voltage scaling and enables full-frame extraction. The proposed design consumes 4.7mW at 400mV and achieves 72% higher energy efficiency than prior work.

We present a self-adapting power management unit (PMU) for ultra-low power wireless sensor nodes. The PMU uses 1.03nF of on-chip MIM capacitance in a reconfigurable switched-capacitor network (SCN) that automatically adapts to different battery voltages for down-conversion and different harvesting sources/harvesting conditions for up-conversion. The PMU achieves 63.8% / 60.7% down-conversion efficiency at 17.9μW active mode / 12.8nW sleep mode power loading. With the adaptive down-conversion ratio, load power range is improved by 3.76× and 5.48× in sleep and active mode, respectively. We show how the proposed adaptation method enables harvesting with solar, microbial fuel cell, and thermal energy sources, increases harvesting efficiency by 1.92× and achieves the peak extraction efficiency of 99.8% for solar cell.