Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation whose result is not used in the downstream circuit, power is being consumed for an otherwise redundant computation. Operand isolation is a technique to minimize the power overhead incurred by redundant operations by selectively blocking the propagation of switching activity through the circuit. This paper discusses how redundant operations can be identified concurrently to normal circuit operation, and presents a model to estimate the power savings that can be obtained by isolation of selected modules at the register-transfer (RT) level. Based on this model, an algorithm is presented to iteratively isolate modules, while minimizing the cost incurred by RTL operand isolation. Experimental results with power reductions of up to 30% demonstrate the effectiveness of the approach.

Functional decomposition is an important technique for technology mapping to look up table-based FPGA architectures. We present the theory of and a novel approach to functional disjoint decomposition of multiple-output functions, in which common subfunctions are extracted during technology mapping. While a Boolean function usually has a very large number of subfunctions, we show that not all of them are useful for multiple-output decomposition. We use a partition of the set of bound set vertices as the basis to computepreferabledecomposition functions, which are sufficient for an optimal multiple-output decomposition. We propose several new algorithms that deal with central issues of functional multiple-output decomposition. First, an efficient algorithm to solve the variable partitioning problem is described. Second, we show how to implicitly compute all preferable functions of a single-output function and how to identify all common preferable functions of a multiple-output function. Due to implicit computation in the crucial steps, the algorithm is very efficient. Experimental results show significant reductions in area.

The growing popularity of look-up table (LUT)-based field programmable gate arrays (FPGA's) has renewed the interest in functional or Roth-Karp decomposition techniques. Functional decomposition is a powerful decomposition method that breaks a Boolean function into a set of subfunctions and a composition function. Little attention has so far been given to the problem of selecting good subfunctions after partitioning the input variables into the disjoint bound and free sets. Therefore, the extracted subfunctions usually depend on all bound variables. In this paper, we present a novel decomposition algorithm that computes subfunctions with a minimal number of inputs. This reduces the number of LUT's and improves the usage of multiple-output SRAM cells. The algorithm iteratively computes subfunctions; in each iteration step it implicitly computes a set of possible subfunctions and finds a subfunction with minimal support. Moreover, our technique finds nondisjoint decompositions, and thus unifies disjoint and nondisjoint decomposition. The algorithm is very fast and yields substantial reductions of the number of LUT's and SRAM cells.

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Article Free Access Share on Reducing power dissipation after technology mapping by structural transformations Authors: Bernhard Rohfleisch Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, GermanyView Profile , Alfred Kölbl Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, GermanyView Profile , Bernd Wurth Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 789–794https://doi.org/10.1145/240518.240667Published:01 June 1996Publication History 25citation233DownloadsMetricsTotal Citations25Total Downloads233Last 12 Months19Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

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In this paper, we present a novel method for topological delay optimization of combinational circuits.Unlike most previous techniques, optimization is performed after technology mapping.Therefore, exact gate delay information is known during optimization.Our method p erforms incremental network transformations, speci cally substitutions of gate input or output signals by new gates.We present new theory which relates incremental network transformations to combinations of global clauses, and show how to detect such valid clause combinations.Employing techniques which originated in the test area, our method i s c apable to globally optimize large circuits.Comprehensive experimental results show that our method reduces the delay of large standard c ell netlists by 23% on average.In contrast to most other delay optimization techniques, area r e ductions are achieved c oncurrently.

We present theory and a novel, implicit algorithm for functional disjoint decomposition of multiple-output functions.While a Boolean function usually has a huge number of decomposition functions, we show that not all of them are useful for multiple-output decomposition.We therefore introduce the concept of preferable decomposition functions, which are sucient for optimal multiple-output decomposition.W e describe how to implicitly compute all preferable decomposition functions of a single-output, and how to identify all common preferable decomposition functions of a multiple-output function.Due to the implicit computation in all steps, the algorithm is very ecient.Applied to FPGA synthesis, the method combines the typically separated steps of common subfunction extraction and technology mapping.Experimental results show signi cant reductions in area.