This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-state-aging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-time-aging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.

We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduces dynamic cooling as one of the self-tuning parameters, in addition to supply voltage and clock frequency. Our optimized self-tuning satisfies performance constraints at all times and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. Our framework features three control policies: 1. Progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2. Progressive-on-state-aging (POSA), which estimates aging by tracking active/sleep mode, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; 3. Progressive-real-time-aging-assisted (PRTA), which estimates the actual amount of aging and initiates optimized control action. Simulation results on benchmark circuits, using aging models validated by 45nm CMOS stress measurements, demonstrate the practicality and effectiveness of our approach. We also analyze design constraints and derive system design guidelines to maximize self-tuning benefits.

Experimental verification of noise models is one of the major challenges in noise modeling. A circuit-based noise characterization technique is introduced which uses phase noise measurement data to extract MOSFET noise parameters. After a brief discussion on MOSFET noise, experimental data is presented on the severity of excess noise in a 0.18μm CMOS process using the proposed technique. It is shown that in this process, the noise power of minimum-channel-length devices is up to 6 dB larger than that of long-channel devices. The proposed technique can be used for model verification as well as for parameter extraction in developing CMOS processes.

An approach for synthesized compact models (SCM) of substrate noise coupling is presented. The model is formulated using parameterized and scalable Z matrix. The improvement in modeling near field effects results in better substrate noise modeling for analog circuits. The geometrical scalability of the model provides a bi-directional link between noise analysis in the post-layout phase for verification and the noise-aware layout synthesis using convex optimization techniques. The model is validated by rigorous EM and device simulations. Several application examples are used to demonstrate the bi-directional usage of the model.

Computer-aided design (CAD) techniques are absolutely essential to harness the ever-increasing complexity of the microsystem design. Similarly, the technology CAD (TCAD) tools played a key role in the development of new technology generations. Although there is a common belief that the TCAD tools have been trailing the technology development, the situation has been changing very significantly especially over the last decade. For the deep submicrometer (DSM) devices, these tools provide a better insight than any measurement techniques and they have become indispensable in the new device creation. Moreover, these tools after calibration to a relatively small number of experiments, exhibit very impressive predictive power, which is utilized to speed up the technology integration and transfer to volume manufacturing. This results in very manufacturable high-yielding products that can be ramped up much faster than in the past decade, which is absolutely necessary given the huge costs of integrated circuit fabrication lines, short product lifecycles and penalties for being late to the market place. In this paper, we present our perspective on the semiconductor technology development, and highlight the rapid growth of TCAD and its strategic use in the semiconductor industry.

Stable and robust finite element methods for the convective hydrodynamic model of semiconductor devices are developed and implemented on distributed memory parallel computers. Specifically, a stable and accurate space-time and Galerkin/least-squares finite element formulation is developed for the hydrodynamic transport equations for the conservation laws. In addition, Galerkin finite element methods are employed for the Poisson and lattice thermal diffusion equations. The inclusion of the lattice thermal diffusion equation in the numerical solution of the convective hydrodynamic model is presented for the first time. Numerical results for a bipolar transistor are included to illustrate the effectiveness of the numerical methods. Numerical simulations of semiconductor devices using the convective hydrodynamic model require a significant amount of computations. A single-program-multiple-data (SPMD) programming model is proposed for the implementation of the hydrodynamic model on distributed memory parallel computers. Employing the SPMD programming model, a serial program developed on a workstation can be converted into a parallel program with minimal changes. The parallel program has been ported to a wide range of distributed memory parallel computers including the iPSC/860 hypercube, the Touchstone Delta machine, and the IBM SP-1. Parallel performance results are reported for a bipolar transistor, silicon MESFET and diodes. The results indicate that the parallel hydrodynamic device simulator exhibits excellent speedups and scalability on distributed memory parallel computers with minimum communication overhead.

Harmonic and intermodulation distortion effects play an important role in numerous analog applications, particularly in such areas as wireless communication systems. In this paper, we present a two-dimensional harmonic balance semiconductor device simulator which accurately models these nonlinear effects at the physical (drift-diffusion) level. The simulator is based on Stanford University's PISCES code, and supports the full range of physical models and features present in the time-domain version of the program. A modified block Gauss-Seidel-Newton nonlinear relaxation scheme is developed to efficiently handle the extremely large size of two-dimensional harmonic balance semiconductor device simulation problems.

A scheme for automated tracing of arbitrarily shaped I-V curves is presented. Tracing out the I-V curves for complicated device phenomena such as breakdown in bipolar transistors and latchup in CMOS structures using conventional device simulation techniques requires a priori knowledge of the shape of the I-V curve and thus is not suitable for exploring new device phenomena. This paper presents a dynamic load-line technique which adapts the boundary conditions as the trace progresses to ensure convergence. By monitoring the slope of the curve, an optimal boundary condition is determined for each point. The boundary condition consists of a voltage source and load resistance corresponding to a load line which is orthogonal to the differential resistance at each point. This orthogonality is defined in a coordinate system scaled by the DC resistance. Step size between points is also defined by this scaling and is varied according to a smoothness criterion. The algorithm guarantees fully automatic tracing of any I-V curve without prior knowledge of the curve's characteristics. Its implementation is completely external to the device simulator, i.e., it simply sets up the boundary conditions to be used by the simulator. Curve tracing examples which validate the algorithm are discussed.>

A robust numerical model for the charge balance condition (CBC) on floating gates (FG) is presented, in which the quasi-Fermi level, instead of the potential (as in conventional models), is assumed to be a constant in the FG. By solving Poisson's equation in the FG region with an extra equation for the CBC, the accurate distribution of both potential and charge can be obtained. A quasi-stationary scheme is developed to simulate the writing or erasing procedure of EEPROM cells, which may serve as a useful tool for accurate simulation of devices such as EEPROMs or EPROMs. Simulation results reveal a significant degradation of tunneling efficiency when N/sub FG/>

An integrated process simulation system which uses functional utilities to integrate disparate 2-D simulation tools is described. The software utilities provide mechanisms for simulator input generation and user interaction, for mapping between different cross-section formats, and for output visualization. The specific utilities are described. With this approach, several process simulators for lithography, etching, deposition, and thermal processing have been integrated into a unified system, SIMPL-IPX (simulation of profiles from the layout-integrated process simulation environment with X-Windows). Simulation examples for metal l planarization, bipolar technology with a polysilicon , collector 5 plug, and advanced lithography are presented to demonstrated 7 the usefulness of this approach to technology CAD tool 8 integration. Methods for improved data management using 9 a CAD framework are described.>

An approximate block elimination (ABE) method for constructing preconditioning matrices in the block iteration of systems of linear equations is presented. Four families of preconditioning matrices based on this approach are identified for solving the 2*2 block equations with the Jacobian resulted from the 3-D one-carrier semiconductor device analysis problem. The fully coupled Newton's method is used as a test case on a parallel computer, the Intel iPSC/2 hypercube. There are ten different preconditioning transformations including the alternate block factorization (ABF) and the modified singular perturbation (MSP) schemes. The results from computational experiments indicate that eight of these preconditioning matrices significantly extend the convergence region of the block Gauss-Seidel iteration process of Newton steps and five of them speed up the convergence with a factor of up to more than an order of magnitude.>

Article Free Access Share on Linking TCAD to EDA—benefits and issues Authors: G. Chin Stanford University, Stanford, CA Stanford University, Stanford, CAView Profile , W. Dietrich Stanford University, Stanford, CA Stanford University, Stanford, CAView Profile , D. Boning Texas Instruments, Dallas, TX Texas Instruments, Dallas, TXView Profile , A. Wong University of California at Berkeley, Berkeley, CA University of California at Berkeley, Berkeley, CAView Profile , A. Neureuther University of California at Berkeley, Berkeley, CA University of California at Berkeley, Berkeley, CAView Profile , R. Dutton Stanford University, Stanford, CA Stanford University, Stanford, CAView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 573–578https://doi.org/10.1145/127601.127735Published:01 June 1991Publication History 5citation247DownloadsMetricsTotal Citations5Total Downloads247Last 12 Months22Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A 3-D device solver (STRIDE), capable of solving grids up to 250,000 nodes, has been developed on a message passing multiprocessor. By the use of iterative matrix solvers and Gummel style nonlinear iteration schemes, user memory per node is reduced over use of direct solvers and Newton schemes. By using an independent-edge-grouping scheme to increase the vector length to the order of the number of variables, the vector processing efficiency is significantly increased without additional floating point operations. The modified-singular-perturbation (MSP) scheme is extended to two-carrier simulations. This significantly speeds up the convergence rate of Gummel style nonlinear iterations. Physical insight gained from the MSP schemes also leads to an automatic switching scheme between various nonlinear schemes based on the monitoring of certain matrix parameters. Application of STRIDE is demonstrated by an analysis of latchup trigger current dependence on layout arrangement.>

A set of programming techniques which can reduce the time required to develop scientific programs is presented. Subroutines are designed to allow every execution path to be tested independently. Checksums are used to compress arrays and groups of variables without losing meaningful debugging information. Invariance assertions on checksums are used to detect incorrect behavior of a program at a place near the source of the error. Traces of checksums of groups of variables are used to monitor the time evolution of intermediate results. By comparing the checksums produced in tracing the program and the checksums produced in tracing a reference copy of the program, errors can be rapidly localized when a program is modified, ported, put in parallel, or optimized for a particular machine.>

An accurate method of simulating nonequilibrium gate current and sheet-carrier concentration in AlGaAs/GaAs HEMT structures is reported. The calculation is based upon self-consistent solving of Schrodinger's equation, Poisson's equation and continuity equations. A concept for three-dimensional electrons accompanied by two-dimensional electrons in a quantum well at a heterointerface makes it possible to solve the continuity equation at the quantum-well region. Thermionic emission theory is applied for the current expression across an abrupt heterointerface. As a result, there is a certain voltage drop across the heterointerface, which helps prevent the creation of the neutral region in the AlGaAs layer. Simulated results explain measured gate-current and channel-conductance characteristics of a HEMT structure.>

The process design aid (PDA), a design environment which bridges the gap between design and specification of semiconductor fabrication processes, is presented. The PDA uses a hierarchical process model supporting reuse of well-characterized process fragments; integrates design goals with process and simulation data in a single knowledge base; and provides direct support for the numerical optimization of process parameters and simulator calibration parameters. Details of a hierarchical, object-oriented process representation are discussed. Results of modeling a 0.8- mu m BiCMOS process with the PDA are presented, demonstrating automatic generation of consistent simulation and manufacturing specifications, efficient incremental simulation, and fast, interactive, closed-loop optimization of process parameters.>

Hot electron effects for n-channel submicron MOSFET devices have been analyzed on the basis of accurate physical models. The PISCES-Monte Carlo scheme is implemented to calculate impact ionization coefficients and predict accurately the generation of electron-hole pairs. The coupling scheme also provides important physical parameters and constants for developing substrate and gate current models as well as an improved mobility model, especially for high drain and gate bias conditions. The analytical models for impact ionization, thermionic emission and mobility are incorporated into the PISCES program and give accurate predictions compared with experimental results. These models predict the peak and saturated transconductance curves for the high drain voltage of LDD MOSFET devices.>

Scattering parameters of wide MOSFET devices have been measured at the wafer level in the frequency range up to 1 GHz. These scattering parameters are converted to Y-parameters for device characterization and compared with SPICE simulations of L-, Pi -, and T-ladder distributed RC circuits taking into account the effect of distributed gates. Good experimental agreement shows that this effect can be modeled appropriately by multisection RC ladders, especially T-ladder circuits. Differences among ladder circuits in modeling this effect are discussed qualitatively.>

The BiPMOS device associated with n-well BiCMOS technologies consumes a substantial area for isolation. A merged BiPMOS device structure is introduced to reduce the device size for BiCMOS VLSI. The performance of the merged BiPMOS device has been analyzed using PISCES-2B, a program for solving Poisson and continuity equations. Comparisons between the merged BiPMOS device and a conventional one show that the merged BiPMOS device, which occupies a much smaller area, has a comparable performance.>

For very small-geometry devices, two-dimensional parasitic effects can be complicated and models with extracted parameters may not be sufficient for accurately analyzing circuit performance. Using a device-level simulator, PISCES-2B, with appropriate boundary conditions, the transient performance of an emitter coupled logic (ECL) inverter with collector-up bipolar transistors of 1 mu m*1 mu m has been analyzed. The propagation delay of this inverter is less than 30 ps for driving an output load of 2 fF with an output swing of 0.8 V at a biasing current of 120 mu A. The speed performance is the result of its buried common emitter structure and its very small collector-to-substrate parasitic capacitances.>

A 3-D one-carrier device solver has been developed on an Intel iPSC2 hypercube multiprocessor which can handle over 130 K nodes. CPU time averages 20 min per bias point on a 50 K-node MOSFET example. Slotboom variables are used in conjunction with the Scharfetter-Gummel current discretization scheme. A scaling scheme is proposed which produces n, p variables from the Slotboom variables. An improved damped-Newton scheme, which maintains the iteration numbers at below fifteen for high gate biases, is used in solving Poisson's equation. The performance of a previously proposed initial guess scheme is improved through the use of a novel update strategy during the Poisson solution stage after the initial guess step. This improvement allows stable calculation for voltage steps as high as 5 V. A modified singular perturbation scheme (MSP) has been proposed whose implementation speeds up the convergence under high-V/sub gs/ and -V/sub ds/ bias conditions by a factor of three to six. A block matrix analysis of the MSP scheme yields insight into its performance.>

The general convergence problems encountered when applying Newton's method to the circuit simulation domain are discussed. The authors identify and explore one source of difficulties for these methods and discuss a solution. The basic transconductance element, widely used to construct FET and bipolar transistor models, results in a pathological failure case for L/sub 2/-based norm-reducing methods due to the unidirectional nature between its input and output mode. Their particular solution retains the generic nature of norm-reducing methods but replaces the L/sub 2/-norm with a nonconsistent point of view. This norm determines which equations should converge first, prioritizes them, and guides the damping of the Newton updates accordingly. From a mathematical point of view, the steepest-descent direction in the Nu-norm is parallel to each Newton update at the iterate point and, therefore, allows more effective damping of the updates. The result has been an order-of-magnitude reduction in the number of Newton iterations. The performance of this norm on a series of high-electron-mobility transistor (HEMT) circuits is presented. The nonconsistency of the Nu-norm and its impact on global convergence properties for norm-reducing methods are discussed.>

A multiwindow, multimethod device analysis algorithm that combines the advantages of efficient drift-diffusion simulators and accurate physical models using Monte Carlo methods is described. The PISCES 2-D device analysis program is used whenever the drift-diffusion model is valid. In situations where the drift-diffusion model breaks down, a window is opened in the part of the device where the hot-carrier effects are important. The Monte Carlo method in the McPOP program is then applied in the window. The simulation results obtained match well with the measured data and the full Monte Carlo results. The CPU time required has been reduced by a factor of 3 to 10 compared with the full Monte Carlo simulation. A parallel Monte Carlo algorithm has been used in the McPOP program. A 20-processor system speeds up the program by a factor of 18.5.>

Hot-electron transport effects in Schottky-barrier diodes grown by molecular-beam epitaxy (MBE) were investigated. Comparisons with experimental results for an Al-n/sup +/ GaAs diode shows that terminal currents obtained using the Monte Carlo (MC) method agree well with experiment and are higher than those of conventional analysis for the forward-bias condition. A much higher thermionic-emission velocity at the Schottky was obtained using the MC analysis compared to previously published results. It is argued that these hot-electron transport effects should be included when analyzing device physics and current-voltage characteristics of Schottky-barrier diodes grown by MBE.>

A program has been developed which efficiently solves the coupled diffusion of interstitials, vacancies, and multiple impurity species in two dimensions. Due to the vast differences in diffusivities of the point defects and impurities, two separate spatial grids are used. A coarse grid is sufficient to represent the rapidly diffusing point defects, whereas a much finer grid is necessary to resolve the details of the impurity profile. Independent time steps are automatically selected for each species, permitting this extremely stiff system of diffusion equations to be solved in acceptable CPU time on a minicomputer. The simulation results are used to study the coupled diffusion of point defects and impurities under local oxidation conditions. Comparison with lap and stain measurements on structures with various widths of oxidizing and nitride-masked regions allows accurate values for numerous point defect diffusion parameters to be extracted.>

Two-dimensional process modeling has been complicated by the increasing complexity of the physical models needed to characterize modern processes. Present physical models for diffusion favor modeling of both the vacancies and interstitials as well as the dopant impurities. these vacancies and interstitials are important in two dimensions since the lateral characteristic lengths are on the order of a few microns, which is comparable to device dimensions. Hence, full two-dimensional solutions of the point defect equations are required to accurately model two-dimensional diffusion. Since the defects diffuse many order of magnitude faster than the impurities, the problem of solving the coupled equations is numerically stiff and the numerical techniques become critical. The numerical methods in SUPREM-IV are described. Since the numerical solutions are time consuming, suitable analytic solutions are considered as an alternative. These analytic solutions are compared to the numerical results to test the limits of the assumptions used in the analytic formulation. The comparison forces the conclusion that analytic solutions are of limited use in prediction of point defect profilesin two dimensions.>

Two-dimensional (2-D) device analysis is coupled into a new model development environment. An improved set of 2-D analytical boundary conditions for submicron MOS technology is developed through using exact information from numerical simulations. In addition to the accurate modeling of 2-D potential boundary conditions, the model provides a framework for further enhancements in the context of technology evolution. Specifically, the methodology is general and can be extended to a variety of technologically complex submicron structures, for example, source/drain tip implants (LDD-type devices) and a variety of other blanket and locally implanted structures.>

A set of algorithms that implement a technique called Supercompaction is described for two-dimensional compaction layouts. The algorithms minimize a one-dimensional objective function (pitch) by moving objects in the layout in two dimensions. The objective function can be monotonically reduced to a locally minimal value, greatly simplifying search. The algorithms can change the layout by simple motion of components or by automatic jog introduction. Experiments shows that: (1) the number of iterations required to reach a locally optimal layout is very small; (2) the time per iteration is competitive with other compaction techniques; (3) supercompacted layouts are smaller in pitch and area than those produced by existing one-dimensional algorithms; and (4) the results of supercompaction are more predictable than those of existing one-dimensional methods.>

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.

The Newton iteration method used in conventional numerical device simulations is extended to include bias conditions as variable parameters in the system of semiconductor equations. This extension leads to a very simple algorithm to evaluate low-frequency, small-signal parameters based on dc solutions. It also provides an elegant way to project an initial guess for subsequent bias conditions. Rigorous mathematical derivation and applications to the evaluation of junction capacitance and breakdown voltage are given. The initial guess projection is also illustrated through examples.

Computer-aided analysis of integrated circuit devices has played a critical role for more than three decades of technology evolution. In the 1950s and early 1960s simulation was used extensively to characterize the operating principles of both bipolar and MOS devices. Bipolar effects such as base-width modulation and base pushout were characterized as well as MOS phenomena including gradual channel and channel-length modulation effects. During the late 1960s and throughout the 1970s simulation provided critical insight in the scaling of devices leading to the advent of very large scale integration (VLSI). Starting in the mid-1970s the modeling of fabrication technology became an important adjunct to device analysis. The need to control threshold and subthreshold behavior of scaled devices played a significant role in this synergistic coupling. Now in the mid-1980s the role of both device and process analysis have each come to new plateaus of both performance and utility. The scaling of submicrometer channel-length MOS devices poses a new set of constraints and challenges. This paper traces the evolution of computer-aided analysis over the past three decades. Unique aspects of the device physics and the role of device and process analysis at each phase of development will be presented. The progression from device conception towards stabilizing the technologies for large-scale product are presented. Problems of submicrometer technology including both production issues as well as new physical requirements for both process and device modeling will be dealt with, including the opportunity presented with the rapid advances in computer technology and the seemingly inevitable computational bottleneck posed by the growing needs for three-dimensional simulation.

In this paper we propose a new algorithm for optimal PLA folding based on a graph theoretic formulation. An efficient best-first search (BFS) algorithm is presented which finds a near-optimal PLA folding. The proposed algorithm first constructs the longest paths on the associated disjoint graph generated from the PLA personality matrix, and then extracts the ordered folding sets from the constructed paths. The algorithm is shown to be effective for most test cases.

This paper presents a novel mathematical formulation to the placement of arbitrarily sized rectangles that simultaneously account for the topological and geometrical characteristics of the placement problem. Special attention is paid to maintain the continuity of the formulation. Two examples are given to demonstrate the performance of the algorithm. Identical placement is obtained from two different initial placements of an example which has 8 movable components and 29 signal nets. For a practical example with 15 movable blocks and 142 signal nets, a final placement which is manual solution comparable is obtained using random initial positions.

A physical basis for parameter extraction of a two-lump bipolar transistor model for high-frequency applications is presented. S-parameter data taken from devices is compared to that generated from a two-lump model predicted by physical theory using 2-D finite element device simulation. Errors within 5 percent in magnitude and 5° in phase are obtained for all four S-parameters for a frequency range up to f/sub T/ and across the full current range. New physical understanding of the effects of dc current flow on high-frequency behavior of bipolar transistors is presented.

This paper examines iterative methods for solving the semiconductor device equations. The emphasis is on fully coupled methods, because of the failure of decoupled methods for on-state devices. Using the PISCES-II device simulator as a vehicle, incomplete factorization and operator decomposition iterative methods are presented for solving the Newton equations. The dependencies of these methods on factors such as choice of variables, bias condition and initial guess are analyzed. The results are compared with sparse Gaussian elimination.

The latchup behavior of a VLSI CMOS technology using hybrid Schottky-ohmic contact sources and drains and a high resistivity substrate has been extensively studied via two dimensional numerical simulation. The modeling allows quantitative explanation of the triggering and sustaining behavior of such structures, as well as an accurate characterization of the influence of the various process and geometrical parameters on the resistance to latchup. The technology is compared to a corresponding low resistivity substrate (epi) CMOS technology.

A methodology for handling a class of stiff multiparticle parabolic PDE's in one and two dimensions is presented. The particular example considered in this work is the interaction and diffusion of two point defects in silicon, interstitials and vacancies. Newton's method, latency techniques, and second-order time-stepping approaches all contribute in significantly reduced computation times. A general class of diffusion-reaction problems is defined and conditions under which the corresponding Newton matrix is invertible and Newton's method converges to a globally unique solution are derived. The convergence properties of the purely reactive system are also derived and compared to those given by a Picard iteration. Application of basic iterative matrix techniques for the general diffusion-reaction system is discussed and specific numerical examples of point defect kinetics are given.

This paper presents a new algorithm to extract resistance values from an integrated circuit artwork description. Instead of trying to solve for the exact resistance values, heuristics are used to find an approximate solution. The algorithm first breaks the input polygons into simple pieces, and then finds the resistance through each piece. This procedure enables the extraction to be both fast and memory efficient. The heuristics used for splitting the polygons and calculating the pieces' resistance are derived from rules of electrostatics, and yield answers that are within 10 percent of the exact resistance values. The operations needed to break complex polygons into simpler pieces are very similar to other geometric operations used in artwork analysis systems.

Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model. An example is presented to show the value of the latch-up model in latch-up threshold prediction. Finally, some latch-up control methods are discussed.