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Henry C. Chang

dblp:35/3302 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Integrated circuit design · 23%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › hardware verification › circuit-level verification
analog circuit verification		 0.011993
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation · DAC 1993
Electronic design automation › hardware simulation
behavioral simulation		 0.011993
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation · DAC 1993
Integrated circuit design
analog and mixed-signal circuits		 0.011993
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation · DAC 1993
Integrated circuit design › analog and mixed-signal circuits › data converters
digital-to-analog converter		 0.011993
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation · DAC 1993

Methods — techniques the papers use, named apart from their topics

behavioral simulation · 0.0SPICE · 0.0
YearPublicationVenuePosition
1993 Analog System Verification in the Presence of Parasitics Using Behavioral Simulation
abstract
In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit.In this paper, we present a methodology for analog system verification in the presence of parasitic using behavioral simulation.When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster.
Edward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli
 DAC2