VLDB 2026 Research / reviewers in the wild / expert
Wenbin Zhang 0011
dblp:35/4073-11
· DBLP profile ↗
5ranked-venue papers
0as first author
5since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 4 · 4 since 2021Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
4 papers |
Network measurement and analytics · 54% Software-defined and programmable networks · 30% Network management and operations · 16% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware accelerators and domain-specific architectures · 67% Cloud and datacenter computing · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 8 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › accelerator offloading
DPU offloading |
1.8 | 2 | 2026 | Holm: A DPU-Based Robust Host-Side Latency Monitoring with Low-Overhead and Selective Full-Coverage · INFOCOM 2026 Accelerating Sketch-based End-Host Traffic Measurement with Automatic DPU Offloading · INFOCOM 2024 |
Network measurement and analytics
sketch-based measurement |
1.6 | 2 | 2025 | Phantom: Virtualizing Switch Register Resources for Accurate Sketch-based Network Measurement · EuroSys 2025 Accelerating Sketch-based End-Host Traffic Measurement with Automatic DPU Offloading · INFOCOM 2024 |
Software-defined and programmable networks
programmable data plane |
1.0 | 2 | 2025 | Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches · IEEE/ACM Trans. Netw. 2024 Phantom: Virtualizing Switch Register Resources for Accurate Sketch-based Network Measurement · EuroSys 2025 |
Cloud and datacenter computing › datacenter operations
datacenter monitoring |
1.0 | 1 | 2026 | Holm: A DPU-Based Robust Host-Side Latency Monitoring with Low-Overhead and Selective Full-Coverage · INFOCOM 2026 |
Network management and operations › performance management
performance diagnosis |
0.8 | 1 | 2024 | Toward Full-Coverage and Low-Overhead Profiling of Network-Stack Latency · IEEE/ACM Trans. Netw. 2024 |
Hardware accelerators and domain-specific architectures › domain-specific accelerator › data processing accelerator
data processing unit |
0.3 | 1 | 2026 | Holm: A DPU-Based Robust Host-Side Latency Monitoring with Low-Overhead and Selective Full-Coverage · INFOCOM 2026 |
Software-defined and programmable networks › network function virtualization
network function deployment |
0.2 | 1 | 2024 | Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches · IEEE/ACM Trans. Netw. 2024 |
Software-defined and programmable networks › programmable data plane
programmable switch |
0.2 | 1 | 2024 | Toward Full-Coverage and Low-Overhead Profiling of Network-Stack Latency · IEEE/ACM Trans. Netw. 2024 |
Methods — techniques the papers use, named apart from their topics
sketch · 2.4optimization framework · 1.5greedy heuristic · 1.5field analysis · 1.5DPU offloading · 1.0register virtualization · 0.9switch-host coordination · 0.8eBPF · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Holm: A DPU-Based Robust Host-Side Latency Monitoring with Low-Overhead and Selective Full-Coverage
Haifeng Zhou, Di Wang 0003, Wenbin Zhang 0011, Dianxing Tang, Zhengyan Zhou, Chunming Wu 0001 |
INFOCOM | 4 |
| 2025 | Phantom: Virtualizing Switch Register Resources for Accurate Sketch-based Network MeasurementabstractSketches have proven to be useful for measuring traffic. They store measurement results in the registers of data plane switches. However, they suffer from the short of switch register resources, limiting their measurement accuracy. Xiang Chen 0017, Hongyan Liu 0001, Zhengyan Zhou, Wenbin Zhang 0011, Hongyang Du 0001, Dong Zhang 0010, Xuan Liu 0006, Haifeng Zhou, Dusit Niyato, Qun Huang 0001, Chunming Wu 0001, Kui Ren 0001 |
EuroSys | 5 |
| 2024 | Accelerating Sketch-based End-Host Traffic Measurement with Automatic DPU OffloadingabstractSketch-based traffic measurement is a crucial building block for monitoring traffic statistics and ensuring the quality of services of end-host applications. However, existing approaches for building sketches in end-hosts exhibit poor packet processing performance or high CPU consumption. In this paper, we propose MPU, which automatically offloads sketch-based measurement to the emerging hardware, DPU. MPU consists of a sketch analyzer that profiles sketch resource consumption and an optimization framework that formulates the offloading problem and maximizes sketch performance on DPU. We implement MPU on the NVIDIA BlueField DPU. Our testbed results indicate that MPU achieves 85% lower per-packet processing latency and 47% higher traffic measurement accuracy when compared to existing approaches. Xiang Chen 0017, Wenbin Zhang 0011, Xin Yao 0008, Zizheng Wang, Hongyan Liu 0001, Qun Huang 0001, Xuan Liu 0006, Haifeng Zhou, Chunming Wu 0001 |
INFOCOM | 3 |
| 2024 | Toward Full-Coverage and Low-Overhead Profiling of Network-Stack LatencyabstractIn modern data center networks (DCNs), network-stack processing denotes a large portion of the end-to-end latency of TCP flows. So profiling network-stack latency anomalies has been considered as a crucial part in DCN performance diagnosis and troubleshooting. In particular, such profiling requires full coverage (i.e., profiling every TCP packet) and low overhead (i.e., profiling should avoid high CPU consumption in end-hosts). However, existing solutions rely on system calls or tracepoints in end-hosts to implement network-stack latency profiling, leading to either low coverage or high overhead. We propose Torp, a framework that offers full-coverage and low-overhead profiling of network-stack latency. Our key idea is to offload as much of the profiling from costly system calls or tracepoints to the Torp agent built on eBPF modules, and further to include a Torp handler on the ToR switch to accelerate the remaining profiling operations. Torp efficiently coordinates the ToR switch and the Torp agent on end-hosts to jointly execute the entire latency profiling task. We have implemented Torp on$32\times 100$Gbps Tofino switches. Testbed experiments indicate that Torp achieves full coverage and orders of magnitude lower host-side overhead compared to other solutions. Xiang Chen 0017, Hongyan Liu 0001, Wenbin Zhang 0011, Qun Huang 0001, Dong Zhang 0010, Haifeng Zhou, Xuan Liu 0006, Chunming Wu 0001 |
IEEE/ACM Trans. Netw. | 3 |
| 2024 | Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable SwitchesabstractThe programmable switch offers a limited capacity of packet header vector (PHV) words that store packet header fields and metadata fields defined by network functions. However, existing switch compilers employ inefficient strategies of encoding fields on PHV words. Their encoding wastes scarce PHV words and may result in failures when deploying network functions. In this paper, we propose Melody, a new framework that reuses PHV words for as many fields as possible to achieve resource-efficient PHV encoding. Melody offers a field analyzer and an optimization framework. The analyzer identifies which fields can reuse PHV words while preserving the original packet processing logic. The framework integrates analysis results into its encoding to offer the resource-optimal decisions. Also, to achieve timeliness at runtime, it provides a Greedy-based heuristic, which quickly solves PHV encoding and returns near-optimal results. We evaluate Melody with production-scale network functions. Our results show that Melody reduces the consumption of PHV words by up to 85%. Xiang Chen 0017, Wenbin Zhang 0011, Hongyan Liu 0001, Jianshan Zhang, Qun Huang 0001, Dong Zhang 0010, Haifeng Zhou, Xuan Liu 0006, Chunming Wu 0001 |
IEEE/ACM Trans. Netw. | 2 |