Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG's), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a predetermined number of arbitrary input vectors. We show that this result holds for test sets derived based on structural and functional methods, and based on the conventional and multiple observation time testing strategies. Furthermore, we derive the conditions under which synchronizing sequences are preserved under retiming. We show that a structural synchronizing sequence for a circuit drives any of its corresponding retimed circuits to an equivalent state. In addition, we show that functional synchronizing sequences are preserved under retiming by adding a prefix sequence of a predetermined number of arbitrary input vectors. The impact of retiming on ATPG complexity and test-set preservation under retiming suggest a new approach for enhancing the performance of structural, sequential ATPG's. Experimental results show that high fault coverages can be achieved on high-performance circuits optimized by retiming with much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

This paper introduces a model which describes the cost of automatic test pattern generation for (non-scan) sequential logic in terms of attributes of the circuit under test. This model addresses a core issue involved in integrated circuit design and test trade-offs, and can be used to evaluate the cost effectiveness of potential design-for-testability (DFT) techniques. This knowledge can also be used to identify hard-to-test portions of designs, and therefore to devise more cost-effective DFT techniques.

The research reported in this paper has been conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation algorithms, which can lead to extremely long test generation times. The retiming transformation is used to create families of circuits which have the same sequential depth and number and length of cycles, but a significantly different percentage of valid states. It was observed for three different sequential test pattern generators that the increase in complexity of test pattern generation is related to a new circuit attribute, termed density of encoding, and not to the sequential depth or number and length of cycles-i.e., those circuit parameters to which the complexity of test pattern generation has traditionally been attributed.

Abstract| Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault eciency attained.In this paper, we show that retiming preserves testability with respect to a single stuck-at fault test set by adding a pre x sequence of a pre-determined number of arbitrary input vectors.Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

The results of implementation studies utilizing commercially available IEEE 802.5 chip sets and boards are reported. Serious implementation flaws were discovered that prevent the full potential of the IEEE 802.5 token ring standard from being realized for real-time applications. Specifically, unbounded delays can be introduced which not only destroy the desired response time determinism offered by algorithmic scheduling, but which also negate asynchronous alert class guarantees and unnecessarily increase other asynchronous response times. An analysis is made of the scheduling properties of current implementations, and modifications to the current implementations are proposed to allow them to realize the full potential offered by the IEEE 802.5 standard for real-time applications.>

The priority-inversion problems in real-time communication are addressed, and solutions developed for the ARTS distributed real-time operating system are presented. The performance results of the multi-thread-based protocol implementation are compared with those of other implementation schemes, and the schedulability is analyzed. Experimental results indicate that the multi-thread-based protocol implementation could eliminate potential priority-inversion problems and also demonstrate the same schedulability as the softint implementation scheme in spite of about 10% additional implementation overhead.>

An approach for scheduling the IEEE 802.5 token ring for hard real-time applications is presented that not only guarantees deadlines for synchronous class messages, but also greatly reduces asynchronous class response times. Highly responsive guaranteed service is introduced for alert class asynchronous messages. Conventional use of the IEEE 802.5 token ring provides synchronous communication services using time-domain multiplexing (TDM) while relegating asynchronous class message services to background status. An algorithmic-based scheduling approach is presented that supports a priori schedulability determination for arbitrary synchronous message sets without the costly time-line development, testing, and tuning associated with TDM techniques. This capability allows the IEEE 802.5 to support dynamic, adaptive and reconfigurable run-time environments where the inflexibility of TDM would be prohibitive. Advanced real-time scheduling applied to the IEEE 802.5 token ring greatly enhances the responsiveness of asynchronous class messages while still maintaining guaranteed service for the synchronous class.>