In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.

The number of Internet users is now increasing rapidly because of the popularity of the WWW. Intra-nets and extra-nets have also become very popular as they enable efficient business processing. Accordingly, there is increasing demand for Internet/intra-net/extra-net services that offer higher speed, shorter delay, higher throughput, and stronger security at lower cost. To satisfy those demands, this paper proposes the network router/bridge concept that acts as a large router/bridge when constructing a nationwide computer network and a cut-through ATM-based forwarding engine (CAFE) that forwards IP packets/Ethernet frames with cell-by-cell processing in the network router/bridge. We also propose a hardware based fast search method to get the address entry table suitable for cell-by-cell processing, one of the key technologies of CAFE.

A situation-based selective video recording system for a short term memory aid is proposed. The system selectively records the images of events which happened in one's daily life based on sensor observation of the user situation. The user wears sensors to monitor the environment and the action of the user himself. Selected scenes viewed with a head-mounted camera are recorded with situation information. This paper reports the system overview and some field experiments.

This paper discusses a new approach to efficient system design verification that uses an FPGA based real-time emulator. The architecture of a real-time emulator suitable for high-speed digital transmission system emulation and an experimental system are described. The proposed system consists of an emulation engine using the custom designed multi-chip module FPGA called PROTEUS-MCM, a program control unit, and a physical interface. The system can be used not only for real-time emulation of high-speed transmission systems, but also as initial systems for actual communication networks.

The paper discusses a new architecture for reconfigurable real time signal transport systems that uses FPGAs and describes an experimental system design. The basic architecture of the reconfigurable transport system is proposed based on the requirements for real time signal transport in a typical telecommunication network. The proposed system consists of reconfigurable modules using the custom designed FPGA called PROTEUS, a program control module for hardware/software coprocessing, and line interface modules including an automatic connection control mechanism. The system can be used not only for the initial installation stages of actual communication systems, but also for rapid prototyping tools or emulators.

A B-ISDN introductory scenario is described from the viewpoint of service, and a virtual-path (VP)-based access network architecture based on this scenario is discussed. In the access network each VP is dedicated to one service, such as a leased circuit, switched circuit, or video distribution. The concept and functions of a subscriber line terminal (SLT) to realize this capability are introduced. Asynchronous transfer mode (ATM) subscriber line system deployment and the main SLT functions are discussed.>

A new polyphase phase-locked oscillator (P-PLO) is proposed which overcomes one of the greatest difficulties in the passive bus configuration: timing extraction from signals in multiplexed channels with different mean phases. The proposed oscillator generates appropriate retiming clock pulses for each channel independent of other channels. Moreover, since pulse overlaps between channels may appear at the first and last bits of each channel, the oscillator shifts retiming clock phases of these bits to avoid sampling overlaps. A performance analysis method extended from the conventional Markov chain model is also proposed. The theoretically obtained jitter and retiming margin characteristics correspond closely to experimental results. This circuit is also shown to be adaptable to point-to-point configurations which, like passive bus, will be used in the ISDN basic interface recommended as one of the 1-series interfaces by CCITT. This allows easy rearrangement of interface wiring, e.g., changing from the passive bus to point-to-point configuration, without any adjustment of the network terminator.