Demo Data from VLDB 2026 / reviewers in the wild / expert
Qian-Yu Tang
dblp:35/466
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 88% Performance modeling and evaluation · 9% Interconnection networks and networks-on-chip · 3% | |
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 100% |
Topics — the 9 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault diagnosis |
0.0 | 2 | 1999 | Diagnosis of clustered faults for identical degree topologies · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 Diagnosis of Parallel Computers with Arbitrary Connectivity · IEEE Trans. Computers 1999 |
Electronic design automation
physical design |
0.0 | 1 | 2000 | Wire space estimation and routability analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation › physical design › routing
routability |
0.0 | 1 | 2000 | Wire space estimation and routability analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation › physical design
routing |
0.0 | 1 | 2000 | Wire space estimation and routability analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation › physical design
wire space estimation |
0.0 | 1 | 2000 | Wire space estimation and routability analysis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Performance modeling and evaluation
asymptotic analysis |
0.0 | 1 | 1999 | Diagnosis of Parallel Computers with Arbitrary Connectivity · IEEE Trans. Computers 1999 |
Electronic design automation › hardware verification and test › fault diagnosis
diagnosis algorithm |
0.0 | 1 | 1999 | Diagnosis of Parallel Computers with Arbitrary Connectivity · IEEE Trans. Computers 1999 |
Electronic design automation › hardware verification and test › fault diagnosis
probabilistic diagnosis |
0.0 | 1 | 1999 | Diagnosis of Parallel Computers with Arbitrary Connectivity · IEEE Trans. Computers 1999 |
Electronic design automation › hardware verification and test › VLSI testing
wafer testing |
0.0 | 1 | 1999 | Diagnosis of clustered faults for identical degree topologies · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999 |
Methods — techniques the papers use, named apart from their topics
probabilistic fault model · 0.0gamma failure distribution · 0.0exponential failure distribution · 0.0bernoulli failure distribution · 0.0stochastic modeling · 0.0poisson distribution · 0.0probabilistic analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Wire space estimation and routability analysisabstractThis paper presents a new stochastic model for two-dimensional layouts of large size. Two problems are addressed. (1) Under the condition that the number of wires emanating from a block is Poisson distributed, determine the distribution of channel width, thus estimating the average channel width. (2) Given T tracks for each channel, determine the success probability of routing an M/spl times/M cell array chip. For both problems, closed formulas are obtained. The experiment demonstrates the effectiveness of our approach. The results can be applied to gate array, field-programmable gate array design, etc. Qian-Yu Tang, Dian Zhou |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1999 | Diagnosis of Parallel Computers with Arbitrary ConnectivityabstractRecently, D. Fussell and S. Rangarajan (1989) considered performing multiple tests to achieve correct diagnosis of constant degree connection structures. They showed that the probability of correctly identifying every processor approaches one as n/spl rarr//spl infin/, where n is the number of processors in the system. In this paper, we give the performance analysis for the probabilistic diagnosis algorithm defined previously. In comparison with previous results, we first derive a different and formal proof for the analytic expression of the probability processor is correctly identified. We then show an exact analytic expression for the probability of the event that a faulty processor is correctly identified. Our result improves the previous results. Based on our new results, we finally give the asymptotic analysis for the algorithm. We demonstrate that the probability of correctly identifying every processor approaches one as n/spl rarr//spl infin/. Qian-Yu Tang |
IEEE Trans. Computers | 1 |
| 1999 | Diagnosis of clustered faults for identical degree topologiesabstractHuang et al, [1998] studied the diagnosis of clustered faults and wafer testing. They proposed a diagnosis algorithm for a probabilistic fault model in simple rectangular grid structures. In this paper, we extend their results and study the diagnosis algorithm for arbitrary identical degree topologies. Our results are useful and valid for a large class of topologies. We investigate the local and global performance of the algorithm under several important fault distributions: Bernoulli failure distribution, Gamma failure distribution, and exponential failure distribution. We demonstrate that the diagnosis scheme can identify almost all nodes successfully even if the percentage of fault-free units is low (much lower than 50%) while almost all units are guaranteed to be correctly identified. In addition, we show that the performance of the algorithm is insensitive to the changes of the percentage. Qian-Yu Tang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |