The dynamics of today's electronics industry introduces enormous pressure on chip designers to come up with chip designs in a very limited time. This is due partly to the short life cycle of application specific products in the marketplace. The availability of powerful graphics processors and microprocessors with processing powers comparable to minicomputers has introduced several stand alone workstations into the design arena. Designer productivity is improved to a great extent by the provision of computer-aided design tools that take a product from concept all the way through test at a single design station. This improvement in productivity is very much felt while designing less complex chips. However, corporations that turn out highly complex chips like 32-bit microprocessors and their peripheral chips still rely heavily on the processing powers of powerful mainframes or supercomputers. It is design cases such as these that will question the adequacy and practicability of introducing workstations into the culture of the compcenter-based design methodologies. To them, workstations represent yet another level of computing power which has to be integrated into the design environment.

This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.