The growing importance of post-silicon validation in ensuring functional correctness of high-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. We propose a unified functional verification methodology for the pre- and post-silicon domains. This methodology is based on a common verification plan and similar languages for test-templates and coverage models. Implementation of the methodology requires a user-directable stimuli generation tool for the post-silicon domain. We analyze the requirements for such a tool and the differences between it and its pre-silicon counterpart. Based on these requirements, we implemented a tool called Threadmill and used it in the verification of the IBM POWER7 processor chip with encouraging results.

Parallelism in system architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. We report on a method for system-level test case generation. This method relies on dynamic interleaving of scenarios from the core level or sub-system level. We discuss the relevance of this method for the system level. We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and power management in the cell processor, as well as verification of the pSeries eServers. We claim that this method shortened the system level verification cycle and allowed reuse in and across projects, which led to exposure of system-level bugs in a relatively short time.