Modern multimedia, gaming and entertainment devices epitomize high-growth, consumer-driven applications for silicon. 2006 has been a year that launched several high-profile gaming systems, and major changes in home networking. This year has also witnessed the emergence of the digital home and the ePC, as well as continued struggles for control of the home gateway. Mobile-digital has continued with the fusion of media, telephony, and digital-mobile TV. The industry's ability to rapidly evolve such consumer-centric systems brings to bear all of the technology competencies required for cutting-edge IC designs, as well as for tools and methodologies that support those designs. Multimedia and gaming chips are pushing the leading edge of EDA technology forward on fronts that include architectural synthesis, high-speed clocking, power management, verification, and IP reuse. As just one example, GPU operations per second are growing significantly faster than desktop CPU operations per second, while at the same time, GPU design teams often place less, emphasis than microprocessor teams on circuits and layout, and more emphasis on architecture and design enablement. The confluence of these trends leads to design and CAD solutions that are unique in the market space. In this panel session, the panelists have been selected to represent five key constituencies: the digital home (Intel), mobile digital TV (Samsung), graphics engines (NVIDIA), advanced displays (Pixelworks), and gaming/multimedia processing (IBM). The panel will address such questions as; what are the underlying chip architectures and roadmaps for key multimedia/entertainment platforms?; what are the key design and technology challenges (or brick walls) for next-generation products, and how will these challenges be addressed?; where will we see the next convergence in devices and platforms?; what other challenges arise from complex supplier and competitor relationships, standards, and other aspects of a globalized market? Other design challenges to be discussed include design enablement (compilers, programming models, etc.), design for IP reuse (configurability, derivatives), and IP management in a world of increasing co-opetition.

Overview Two years ago, DAC-2001 attendees enjoyed a thrilling debatepanel, “Who’s Got Nanometer Design Under Control?”, pitting sky-is-falling Physics die-hards against not-to-worry Methodology gurus. Then, the DAC audience overwhelmingly voted the match for the Methodologists. Now, we've just gone through the biggest business downturn in the industry's history, and we're hearing more and more about chip failures due to 130nm physical effects. Both physics and economics are a lot worse than we thought two years ago. Where are those simple, correct-by-construction methodologies for signal integrity, power integrity, low-power, etc. that we were promised? Were we bamboozled by glib promises from those Methodologists? In this session, we bring back the panelists from two years ago, not for another debate, but to hear well-reasoned perspectives on how to prioritize spending to address nanometer design challenges. Yes, methodology can solve any problem – but now we want to know which problems, in what priority order, at what cost. The panel will address the following questions. • What are the economic impacts and significance of the key nanometer design challenges, relative to each other? • Which nanometer design problems merit responsible R&D investment, in what amounts and proportion? • What is the likelihood of success, both near-term and longterm, in solving key nanometer design challenges? • Where will the answers come from? To keep the discussion very concrete, each panelist will be given a $100 budget, and must defend their allocation of this budget to attack various design problems. Where should the $100 be spent? The audience will determine the best-reasoned allocation, and the winning panelist keeps all the money.

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We will discuss optimization techniques such as clock skew scheduling which can be effectively used to push performance in a power neutral way.

Article Share on There is life left in ASICs Authors: Leon Stok IBM TJ Watson Research Center, Yorktown Heights, NY IBM TJ Watson Research Center, Yorktown Heights, NYView Profile , John Cohn IBM Micro-Electronics, Essex-Junction, VT IBM Micro-Electronics, Essex-Junction, VTView Profile Authors Info & Claims ISPD '03: Proceedings of the 2003 international symposium on Physical designApril 2003 Pages 48–50https://doi.org/10.1145/640000.640013Online:06 April 2003Publication History 6citation300DownloadsMetricsTotal Citations6Total Downloads300Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The exploding complexity of new chips and the ever decreasing time-to-market window are forcing fundamental changes in the way systems are designed. The advent of Systems-on-Chip (SoC) based on pre-designed intellectual-property (IP) cores has become an absolute necessity for embedded systems companies to remain competitive. Designing an SoC, however, is extremely complex, as it encompasses a range of difficult problems in hardware and software design. This paper explains a wide range of SoC issues including market drivers and trends, technology and integration aspects, early architecture definition, methodology, hardware and software design and verification techniques.

This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

As fabrication technology moves to 100 nm and below, profound nanometer effects become critical in developing silicon chips with hundreds of millions of transistors. Both EDA suppliers and system houses have been re- tooling, and new methodologies have been emerging. Will these efforts meet the challenges of nanometer silicon such as performance closure, power, reliability, manufacturability, and cost? Which aspects of nanometer design are, or are not, under control? This session will consist of a debate between two teams of distinguished representatives from EDA suppliers and system design houses. Which side has the right answers and roadmap? You and a panel of judges will decide!

Often, the most interesting tools, methodologies, and insights come from designs that push hard on the “leading edge” of technology--what the survivors commonly call the “bleeding edge” of design. In this session, we collect three such on-the-edge designs, each done in a different style, each aimed at a very different market, each with its own unique set of challenges and solutions. All designers worry about complexity, about time-to-market, about correctness. But these designs go past the sorts of problems many of us have today, and offer some glimpses of problems and solutions we may all be facing tomorrow.

Article Free Access Share on Layout tools for analog ICs and mixed-signal SoCs: a survey Authors: Rob A. Rutenbar Dept. of ECE, Carnegie Mellon University, Pittsburgh, Pennsylvania Dept. of ECE, Carnegie Mellon University, Pittsburgh, PennsylvaniaView Profile , John M. Cohn IBM, Essex Junction, Vermont IBM, Essex Junction, VermontView Profile Authors Info & Claims ISPD '00: Proceedings of the 2000 international symposium on Physical designMay 2000 Pages 76–83https://doi.org/10.1145/332357.332378Online:01 May 2000Publication History 32citation1,208DownloadsMetricsTotal Citations32Total Downloads1,208Last 12 Months23Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The authors describe novel techniques for simultaneous device placement and detailed routing of analog cells. Both nets and devices are treated as placeable, malleable objects in a common simulated-annealing framework. A detailed routing abstraction called a k-bend net limits the complexity of each net's topology, and allows simple incremental net reshaping during annealing. Analog layouts in which the critical interacting nets are simultaneously embedded during device placement prove to be superior, in terms of performance-limiting crosstalk violations, to sequentially placed and routed layouts.>