A novel architecture is presented for a optoelectronic hybrid packet-switching system (HYPASS) for the distribution of multiple-bit-rate broadband services. HYPASS is based on an input-buffered/output-controlled arbitration protocol. This packet switch uses novel multiwave-length optical networks to accomplish routing and transmission of the packets. This system is specifically adapted to utilize the strengths of both optical and electronic technologies.>

An architecture is presented for an optoelectronic hybrid packet switching system (HYPASS) for the distribution of multiple-bit-rate broadband services. HYPASS is based on an input-buffered/output-controlled arbitration protocol. The internal routing and interconnection utilizes a passive optical transport network with wavelength-tunable laser transmitters and fixed wavelength receivers. The single-stage multiwavelength optical interconnect provides an internally nonblocking network for large throughput routing of the bit-serial optical signals. An internal optical control network, with fixed-wavelength trouble receivers, sends output port information to the input nodes for arbitration and control. Packet buffer storage and control processing is performed by word-parallel electronic circuitry. The characteristics and device requirements for this design are presented along with results of a performance analysis of the arbitration and control protocol.>

This paper gives a broadband (total throughput approaching 1 terabit/s) self-routing packet switch design for providing flexible multiple bit-rate broadband services for an end-to-end fiber network. The switch fabric for the slotted broadband packet switch delivers exactly one packet to each output port from one of the input ports which request packet delivery to that output port. The denied requests would try again during the next slot. We discover an effective scheme, implemented by CMOS VLSI with manageable complexity, for performing this function. First, each input port sends a request for a port destination through a Batcher Sorting network, which sorts the request destinations in ascending order so that we may easily purge all but one request for the same destination. The winning request acknowledges its originating port from the output of the Batcher network, with the acknowledgment routed through a Batcher-banyan selfrouting switch. The acknowledged input port then sends the full packet through the same Batcher-banyan switch without any conflict. Unacknowledged ports buffer the blocked packet for reentry in the next cycle. We also give several variations for significantly improved performance. We then study switch performance based on some rudimentary protocols for traffic control. For the basic scheme, we analyze the throughput-delay characteristics for random traffic, modeled by random output port requests and a binomial distribution of packet arrival. We demonstrate with a buffer size of around 20 packets, we can achieve a 50 percent loading with almost no buffer overflow. Maximum throughput of switch is 58 percent. Next, we investigate the performance of the switch in the presence of periodic broadband traffic. We then apply circuit switching techniques and packet priority for high bit-rate services in our packet switch environment. We improve the throughput per port to close to 100 percent by means of parallel switch fabric, while maintaining the periodic nature of the traffic.

A modification to the access policy for ETHERNETTMVersion 1.0 is proposed. By placing additional restrictions (compared with ETHERNET) on each station that is attempting to transmit, this access policy makes it more likely a successful message transmission will occur, and in less time, than the published Version 1.0. Theoretical analysis substantiates these claims.

A transmitter sends packets over a local area network to a receiver. The receiver has a finite amount of storage capacity for buffering messages. A sliding window protocol is employed to insure all packets are delivered without error in order of arrival. Mean throughput rate and packet delay statistics are studied as a function of model parameters. Simulation data are presented.

A transmitter breaks a message up into packets and transmits the packets to a receiver over a single virtual circuit within a local area network. The receiver has a finite amount of storage capacity for buffering messages. A sliding window protocol turns the transmitter on and off to ensure there is always storage room in the receiver for packets. Mean throughput rate and delay statistics are studied as a function of model parameters.

Information is transmitted over a digital link in repetitive time intervals called frames; each frame consists of one or more time slots. Theoretical performance limitations of a variety of time-division multiplexing policies for models of synchronous and asynchronous message streams are studied.

Offices handle a mix of jobs, with each job consisting of one or more steps. The fundamental ingredients in performance analysis are the job arrival statistics, the service required for each job step, and a scheduling policy, for a given equipment configuration. The approach is hierarchical and can be refined in numerous ways; here the authors focus on a mean value analysis: the inputs are the mean times required to execute each step of each job. A series of examples illustrate how these ingredients can be used to upper bound the mean throughput rate and lower bound the mean delay associated with each job type.

A set of stations wish to transmit messages to one another over a shared link. Messages are generated either according to so called finite source or infinite source arrival statistics. The message lengths are independent identically distributed random variables. Two policies for arbitrating contention are compared: polling, and carrier sense collision detection. The maximum mean throughput rate and mean message delay is calculated as a function of model parameters.

We consider a simple model of a multiprocessor digital system, with three main ingredients: a load of different transaction types with given arrival statistics, an architecture consisting of a network of loosely coupled nodes with tightly coupled symmetric multiple processors at each node, and a load partitioning or assignment of each step of execution of each transaction type to a given node. In order to quantify this problem, we adopt a Jackson network for ease of analysis. Our goal is to consider tradeoffs between the workload, the architecture, and workload partitioning to maximize performance. We measure performance by two indices, the mean throughput rate of completing each tran saction type, and the mean response time to completely execute each transaction type. We present analytic formulae for the mean response time for a job assuming simple Poisson arrival statistics. To illustrate the many tradeoffs possible, we consider one example in detail. We show that if we fix the total mean instruction rate, the mean response time for the multiprocessor network is always greater than the mean response time for a job submitted to one equivalent fast processor. In the special case of purely random arrivals and equalutilization of all network nodes, the mean response time will be at least N times that of a single equivalent fast processor. Moreover, the optimum assignment of excess processing capacity to each node to minimize mean response time does not obey a simple linear proportionment based on utilization, but rather a square root assignment of excess capacity. This model accounts for randomness in arrival and service patterns. Significant features left out of this analysis are the system overhead in coordinating all the multiprocessor interactions, memory contention, and so forth, which presumably will only further degrade performance. In many applications, other issues, such as flexibility, reliability, cost, and so forth, may play a dominant role in a design decision; here we concentrate solely on the system response time as the performance measure, with a fixed total instruction rate.

A time division packet switch capable of concurrently handling both voice and data traffic is proposed, and some of its performance limitations are analyzed. The voice packet traffic is handled at a higher priority level than data traffic, in order to meet stringent timing criteria, and can be shown to be handled just as if it were circuit switched. The data traffic utilizes whatever time slots are not occupied with voice traffic. The principal performance limitations described in this exploratory study are the fraction of time the voice traffic is blocked due to all the available time slots already being used for voice traffic, and an upper bound on the mean delay encountered by the data traffic as it waits to find an available time slot. An illustrative numerical result is the following. If we assume that each voice telephone conversation lasts for a mean of five minutes, and that twenty voice calls are generated over a six hour time span, and each data session lasts for a mean of forty minutes, and that five data calls are generated over a six hour time span, then if separate line switched networks are used for voice and for data with long term blocking probability of one percent, a total of 703 64 kbits links would be required to support 461 voice stations and 882 data terminals. On the other hand, using the integrated voice/data switch described here, and if we assume that the total delay due to the switch alone for data packets cannot exceed a long term mean value of one second, then only 298 64 kbit/s links are required to support 461 voice stations and 882 data terminals, reducing the number of required links by a factor of about two. Moreover, the assumptions leading to this comparison suggest that the packet switch could in fact support significantly more than this number of voice stations and data terminals. This is achieved at the expense of additional buffering for the data in the packet switch approach.

Some important ingredients of a switching system are a switching network, a switching network controller, a set of receivers that will process the call before a connection is completed, and a receiver controller. Here a highly simplified analytically tractable mathematical model of such a system was studied to gain insight into performance limitations and to shed light on analytical difficulties in extending the analysis to more realistic systems. For simplicity, it is assumed that each call on arrival must be assigned to one ofSchannels or paths or links (there is no concentration); if no channel is available, the call is cleared from the system. In addition, each call temporarily requires a receiver for setting up its further routing; if no receiver is available, calls queue until a receiver is available. The equilibrium probability of blocking and mean throughput rate, and the equilibrium waiting time distribution are found in terms of model parameters. Numerical results are presented as well as asymptotic analytic results. Using this analysis, the capacity of the switching node is analytically calculated, with the capacity determined by the joint choice of number of links and receivers. The analysis shows in terms of formulas and for selected numerical results that there are cases where one cannot independently choose the number of links and receivers to achieve a desired level of performance.