This work presents a 2-MS/s 18-bit successive-approximation-register analog-to-digital converter (ADC). Acapacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) are cascaded to avoid the linearity limitation caused by parasitic capacitors on the bridge capacitor between the CDAC and the RDAC. An optimal-combination-algorithm (OCA)-based calibration is adopted to improve the linearity of the CDAC and the matching between CDAC and the bridge capacitor, and a least significant bit (LSB)-side dynamic element matching (DEM) strategy is applied to further improve the CDAC linearity. As for the RDAC, this work makes it calibration free by combining the parallel R-unit and R-2R topology. Measurement results show that the proposed ADC can achieve 91.4-dB signal-to-noise and distortion ratio (SNDR), 12.0-parts-per-million (ppm) (3.1-LSB) integral non-linearity (INL), and 174.0-dB FOMS,SNDR(including the power consumed by the calibration logic), and the worst-case INL across 25 dies improves from 72.5ppm (19.0LSB) to 18.8ppm (4.9LSB) after the OCA-based calibration and theLSB-side DEM. To the best of the authors’ knowledge, this is the first high-precision (resolution$\geq 16$bit) data converter adopting OCA-based calibration.

In analog circuit design, transistor sizing remains a critical challenge due to high-dimensional parameter spaces and expensive simulations. While Bayesian optimization shows promise, existing methods struggle with the "curse of dimensionality." Inspired by expert designers’ workflow of focusing on key parameters first before gradually optimizing secondary parameters, we introduce DIVE (Dynamic Information-guided Variable Expansion), a framework that reformulates parameter optimization as an information efficiency maximization problem. Unlike approaches that explore all parameters simultaneously, DIVE progressively includes design variables with the highest information content. Our framework introduces three innovations: (1) constraint-aware weighted mutual information analysis that evaluates parameters’ contributions to objectives and constraints; (2) an adaptive variable inclusion mechanism that determines when to expand the optimization space; and (3) a mutual information-guided kernel learning strategy for Gaussian process models. Evaluations across multiple analog circuits demonstrate that DIVE achieves a 1.61×-21.11× reduction in required simulations while delivering up to 2.69× spec improvements over the state-of-the-art methods. By progressing from simple to complex parameter spaces based on information theory, DIVE establishes a new paradigm for reaching deeper optima by mimicking experienced designers’ design philosophy in circuit optimization. Our code is available1.

Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing.1

In this paper, a 402 MHz reconfigurable regulating rectifier (R3) with a wide input dynamic range has been designed for wireless power transfer (WPT) systems. The rectifier has a 6-stage cross-coupled (CC) rectifier driven by a differential RF input. With the assistance of the analog regulation circuit, the rectifier achieves a regulated 1.8V DC output voltage with a ripple factor of less than 0.07%. Moreover, a digital control logic is employed to modify the stages of the R3to balance the voltage conversion ratio (VCR) and power conversion efficiency (PCE) according to the input signal. The proposed R3can achieve a VCR of 3.66 at a load of 500 kΩ and a PCE of 60.1% at -11.3 dBm output power.

Bootstrapped switches are extensively used in applications demanding high-speed and high-linearity sampling. Nevertheless, the mathematical analysis of distortions caused by parasitic effects has not been performed previously. This paper essentially analyzes three factors that affect the linearity of the switch: source-drain exchange, parasitic capacitive division, and charge redistribution. By employing the time-domain waveform integration technique along with Chebyshev polynomials, the Fourier series expression for on-resistance of the switch can be effectively elucidated. Consequently, the effects of all sources of distortion have been quantified individually. It has been found that both the on-resistance and the bootstrap capacitor has a quadratic effect (40 dB/dec) on the third-harmonic distortion of the sampled signals. A$1\times 9$bootstrapped switch array has been fabricated using 180 nm technology to verify the proposed calculation model. Using the subsampling method, the measured total harmonic distortion (THD) performance was found to be highly consistent with the model calculation results, demonstrating the effectiveness and accuracy of the calculation model. The proposed calculation model will be highly beneficial for designers of bootstrapped switches.

In this article, we propose Img2CAD, the first approach to our knowledge that uses 2-D image inputs to generate computer-aided design (CAD) models with editable parameters. Unlike existing artificial intelligence (AI) methods for 3-D model generation using text or image inputs often rely on mesh-based representations, which are incompatible with CAD tools and lack editability and fine control, Img2CAD enables seamless integration between AI-based 3-D reconstruction and CAD software. We have identified an innovative intermediate representation called structured visual geometry, characterized by vectorized wireframes extracted from objects. This representation significantly enhances the performance of generating conditioned CAD models. In addition, we introduce two new datasets to further support research in this area:a big cad model dataset (ABC)-mono, the largest known dataset comprising over 200 000 3-D CAD models with rendered images, andKOCAD, the first dataset featuring real-world captured objects alongside their ground truth CAD models, supporting further research in conditioned CAD model generation.

In the era of immersive consumer electronics, such as AR/VR headsets and smart devices, people increasingly seek ways to express their identity through virtual fashion. However, existing 3D garment design tools remain inaccessible to everyday users due to steep technical barriers and limited data. In this work, we introduce a 3D sketch-driven 3D garment generation framework that empowers ordinary users - even those without design experience - to create high-quality digital clothing through simple 3D sketches in AR/VR environments. By combining a conditional diffusion model, a sketch encoder trained in a shared latent space, and an adaptive curriculum learning strategy, our system interprets imprecise, free-hand input and produces realistic, personalized garments. To address the scarcity of training data, we also introduce KO3DClothes, a new dataset of paired 3D garments and user-created sketches. Extensive experiments and user studies confirm that our method significantly outperforms existing baselines in both fidelity and usability, demonstrating its promise for democratized fashion design on next-generation consumer platforms.

Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.

Accurately distinguishing between action-related features and non-action-related features is crucial in spatio-temporal action detection tasks. Additionally, the calibration and fusion of information across different modalities remain challenging. This paper proposes a novel Motion Sense and Semantic Correction framework (MS-SC) to address these issues. The MS-SC framework achieves accurate detection by fusing features from images (spatial dimension) and videos (spatio-temporal dimension). A Motion Sense Module (MSM) is proposed to significantly increase the feature distance between action and non-action features in the semantic space, enhancing feature discriminability. Considering the complementary nature of information across different modalities, an efficient Semantic Correction Fusion Module (SFM) is introduced to facilitate interaction between features of distinct modalities and maximize their complementary information integration. To evaluate the performance of the MS-SC framework, extensive experiments were conducted on two challenging datasets, UCF101-24 and AVA. The results demonstrate the effectiveness of the MS-SC framework in handling spatio-temporal action detection tasks.

This work proposes a fabrication and optimization process of miniature Ag/AgCl reference electrodes (RE) at a micrometer (µm) scale for the miniaturized chemical sensors, and these electrodes could also be integrated into a single CMOS chip with solid-state sensors, e.g., ISFET. The thin silver films are first grown by magnetron sputtering and chemically chloridized afterward to form the Ag/AgCl microelectrodes. Different chlorination durations and current densities have been applied to investigate the best fabrication recipe. Both scanning electron microscope (SEM) and energy dispersive spectroscopy (EDS) have been used to analyze the physical composition of electrodes under different recipes. The electrical performance of the proposed micro-electrode has been compared with a standard saturated calomel electrode (SCE), and it is observed that the electrode fabricated with an optimized recipe could provide less than 4 mV accuracy within the pH range from 4 to 10 and more than 200 minutes product life even with only 1.95 × 105µm2area.

In this paper, a voltage-mode-based fully integrated resonance regulating rectifier (IR3) running at 400 MHz has been designed for wireless power transfer (WPT) implants in deep tissue. Separate on-&-off delay compensation circuits are designed to avoid reverse current for efficiency and lower ripple factor, which is about 0.28% at 1.8 V regulated output voltage. With the regulation compensation circuit and the delay compensation scheme, this rectifier can reach a voltage conversion efficiency (VCE) of 1.73 to overcome the low coupling coefficient due to the deep implant, and the whole system achieves a power conversion efficiency (PCE) of 67.8% with 2 mW load.

In this paper, a continuous-time delta-sigma ADC with an integrated ISFET sensor has been proposed for high-resolution biochemical sensing applications. The ADC is designed as a 2nd-order system working under a 256 oversampling ratio, and the ISFET sensor performs as a part of the first gm-C integrator in the system loop. A 1-bit quantization and a DAC feedback, along with a lowpass RC filter, have been implemented to alleviate the linearity challenge. The phase-delay impact of the additional lowpass filter has been compensated by adjusting the weights of different signal paths in the loop. Besides, the noise-shaping effect can be even further enhanced by increasing the weight of the slow path. Simulated in a 180 nm CMOS process, the proposed ADC can achieve an SNDR of 98.78 dB with a bandwidth of 100Hz, consuming 2.5 uW from 1.8 V supply, resulting in 174.8 dB FoMs. This performance has included the ISFET sensor.

In this paper, a front-end interface for capacitive MEMS microphone has been designed and optimised for all PVT corners, which are 1.6V to 3.6V supply voltages, −40°C to 125°C temperature range and comprehensive process variation. It consists of a source follower as the input buffer and a chopper-stabilized amplifier as a calibration stage. To handle the low-noise and high-dynamic-range requirements at the same time, temperature-dependent current biasing and common-mode splitting techniques have been adopted. Verification has been done via post-layout simulations, and the proposed frontend implemented in$\mathbf{0}.\mathbf{18}-\mu \mathbf{m}$CMOS process achieves 68.9dB SNR with 94 dBSPL input and 124 dBSPL AOP at worst scenarios with a typical −38dBV/Pa microphone. Besides, the proposed system eliminates the necessity of LDO, which could further lower the power consumption.

In this paper, a low-power capacitively coupled analog frontend with programmable high-pass cutoff frequency from 61 mHz to 3.4 Hz is proposed. The DC operating point of the input differential pair is settled by dynamic equilibrium of direct tunneling current. A DC servo loop (DCSL) based on duty-cycled operational transconductance amplifier (DC-OTA) has been implemented at the output nodes of the main frontend so that its impedance will not be affected. A minimum of 1.67 pA/V effective transconductance has been realized through the DC-OTA techniques in DCSL, which enable the frontend to achieve 61 mHz high-pass cutoff frequency with only a 10 pF on-chip capacitor. The frontend is implemented in standard$\mathbf{0.18}- \mu \mathbf{m}$CMOS process and it consumes$\mathbf{2.72} \ \mu \mathbf{A}$current in total, achieving a noise efficiency factor of 6.01 in 25 kHz bandwidth (61 mHz - 25 kHz).

This paper presents a top-to-bottom element-matching strategy based on a full-permutation bisection algorithm for data converters. By bisecting the composing elements and recombining them for a minimal weight difference, the linearity of the data converter can be significantly improved. Three different approaches have been implemented for the proposed algorithm, and they are based on linear programming, stochastic quantization, and maximal linearly independent subset (MLIS) respectively. Their pros and cons have been discussed and simulated exhaustively, and all of them have been silicon proved via capacitive digital to analog converters in 180-nm technology. Measurement results of twenty dies for each approach verified the aforementioned theoretical analysis, and all three approaches could achieve sub-30 ppm for all codes after calibration. The worst integral nonlinearity at the most significant bit after calibration can be improved from 402 ppm to 10.9 ppm, which is equivalent to a 5.2-bit boost, indicating a promising potential of the proposed matching strategy. Besides, the MLIS-based approach is the first optimal-combination-algorithm-based matching strategy that achieves$\mathcal {O}(N)$time complexity, as the authors know.

The inevitable capacitor mismatch due to the process variation is one of the major bottlenecks in high-resolution ADC (Analogue to Digital Converter) design. In this work we propose a new compensation strategy which adopts the DEM (Dynamic Element Matching) technique to conventional cyclic ADCs with minimum hardware cost. Theoretical analysis has been done first, and to the best of authors’ knowledge, it is the first time that the relation of the capacitor mismatch, output deviation and THD (Total Harmonic Distortion) has been mathematically established. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. Based on that we further analyse the effect of DEM in frequency domain, which effectively performs a harmonic shaping function to the original output spectrum. Simulation results show that the DEM compensation strategy can effectively boost the worst SINAD (Signal to Noise and Distortion Ratio) Figure from 68.8 dB to 89.5 dB (99.7% yield) under 0.1% capacitor mismatch and 32× oversampling ratio scenario.

In this paper we propose a novel high-resolution chemical sensing front-end with integrated sigma delta quantisation, and the chemical sensing capability is realised by the intrinsic passivation layer. A charge transfer amplifier with adjustable pre-amplification has been adopted to not only transmit the chemical signal to the next sampling stage, but also alleviate the kT/C thermal noise requirement. A pseudo-resistor is added to provide the DC operating points for the front-end, and it is implemented via a MOS transistor applying direct tunnelling effect to achieve huge resistance value. Simulation results show that through oversampling and noise shaping functions, the final resolution can reach up to 90.1 dB even with a 0.3V input signal, making it suitable for applications requiring high-precision chemical detection.

Element matching approaches based on Optimal Combination Algorithms (OCAs) are methods that try to calibrate element mismatches in data converters by rearranging the mapping relations between circuit elements and control logics. This work for the first time proposes a universal method and its corresponding Figure-of-Merit to evaluate the performance of various OCA approaches. It adopts the quantile of integral nonlinearity as the criterion and is consequently compatible with most of matching OCAs. Dynamic performance and the corresponding effective-number-of-bits (ENOB) limited by mismatches are also investigated. A critical feature of the proposed method is its robustness to the disturbance of element standard deviation as long as the standard deviation is in a reasonable region. Merits of our method have been explained and proved mathematically, and also been verified numerically by data extracted from previously reported works and their reproduction by authors, which together make this proposal more convincing and rigorous. Due to those merits, our proposed method could also help designers to specify a feasible standard deviation for circuit elements when they are designing data converters with OCAs.

In this paper, the principle of direct tunnelling current is applied to eliminate the trapped charge in the passivation layer of CMOS ISFETs. A two-transistors frontend is implemented to achieve the most compact structure. For each ISFET the gate voltage will stabilise to a self-settled point regardless of its initial voltage (trapped charge) after reaching a balance between two tunnelling currents, from gate to source and from gate to drain. We have demonstrated the effects of different transistor sizes to this charge cancellation process. And based on above mentioned frontend, by adopting a feedback circuit to control the magnitude of the gate tunnelling current, the velocity of the cancellation process can be controlled. Test results show that the total duration of the process can be manipulated in 2 orders of magnitude. In addition to that, this design essentially performs a high-pass filter with cutoff frequency tunable from 14mHz to 0.3Hz approximately.

In this paper the usage of an on-chip metal electrode for CMOS ISFET has been analysed. It is firstly shown that metal electrode can not provide constant potential as other conventional electrodes. Besides that this paper demonstrates the ions distribution and its corresponding deviated potential when ISFETs are detecting extreme small volume. Finally a 2-D simulation result indicates the potential gradient when a vertical on-chip electrode is applied and suggests that a minimum distance of 2um is desired for robust ISFET design with on-chip electrode.

This paper introduces the use of a diode-connected MOSFET as a temperature controlled switch for trapped charge cancellation of ISFET sensors. The current flowing through the reverse-biased diodes of 2.7 aA is negligible at low temperature but reaches 23 fA when heated to 100°C, which allows for low temperature readout and high temperature compensation of trapped charge. The diode-connected device is tied to the floating gate of the ISFET which is integrated as part of a source-follower readout. The in-pixel feedback loop uses a comparator to turn off the polysilicon heaters once the offset has been cancelled, triggering the readout by switching the op amp into a buffer configuration. Simulations show that the system is calibrated in 35s and the output sensitivity reaches 27.74 mV/pH. The pixel output then tracks any ionic change at its surface without sensor offset.

We demonstrate a CMOS-based lab-on-chip platform which is capable of ion imaging to detect a variation in hydrogen, potassium and sodium ions. An ISFET array is used to detect a change in ion concentration with a calibration scheme to cancel the offset due to trapped charge. The Si3N4passivation layer confers an inherent sensitivity to the sensors, and additional polymer membranes are pipetted containing a potassium and sodium ionophore. An initial algorithm identifies the sensitivity of each pixel towards the target ions. The user can inject a solution with a given concentration of ions and observe the real-time output change of the array on a MATLAB interface. The display then provides an estimate of the target ion concentration.

In this paper, we present a novel approach to ISFET arrays which allows the conception of ion imaging Lab-on-CMOS platforms. K+ and Na+ selective polymer membranes are deposited on the surface of the array so that each pixel is selective to a particular ionic species. An initial calibration produces an accurate mapping of the array in terms of ion-selective regions and determines the sensitivity of the membrane. The system exhibits K+ and Na+ sensitivities of respectively 51.2 mV/dec and 46.8 mV/dec, and demonstrates good discrimination of Potassium and Sodium ions for a common solution exposed to the chip, with a reported error lower than 1%. This ISFET-based tri-ion imaging array constitutes the basis for a portable integrated multi-ion platform.

This paper presents an FPGA based DNA comparison platform which can be run concurrently with the sensing phase of DNA sequencing and shortens the overall time needed for de novo DNA assembly. A hybrid overlap searching algorithm is applied which is scalable and can deal with incremental detection of new bases. To handle the incomplete data set which gradually increases during sequencing time, all-against-all comparisons are broken down into successive window-against-window comparison phases and executed using a novel dynamic suffix comparison algorithm combined with a partitioned dynamic programming method. The complete system has been designed to facilitate parallel processing in hardware, which allows real-time comparison and full scalability as well as a decrease in the number of computations required. A base pair comparison rate of 51.2 G/s is achieved when implemented on an FPGA with successful DNA comparison when using data sets from real genomes.

This paper presents an automatic calibration system for ISFET chemical sensing arrays to tune out any mismatch in sensitivity. Through exploitation of the high frequency spectrum of the sensed signal which does not contain any chemical reaction information, local sensitivity is examined and then calibrated through a successive approximation control mechanism and an 8-bit variable gain amplifier to provide high accuracy tuning. The total calibration process contains three phases, peak detection, AGC through a SAR and finally sensor readout of the detected chemical signal. Designed in a typical 0.35μm CMOS process, the system is capable of compensating a sensitivity deviation of up to 24% in an ISFET array, constraining the error to just 1.5%.

In this paper we propose a low-power, compact ISFET interface capable of overcoming problems of DC offset due to trapped charge and transcoductance reduction due to capacitive division, which commonly exist with implementation in CMOS. Through direct feedback to the floating gate and a low-leakage switching scheme, all the unwanted factors are eliminated while the output is capable of tracking a pH reaction which occurs at the sensing surface. The circuit has been designed to be an inherently constant-voltage-constant-current structure, avoiding any loss of sensitivity due to capacitive division. Additionally, a tradeoff between noise and stability is presented for optimum choice of capacitors. The proposed ISFET and interface has been designed in a typical 0.35 μm process, has an area 60 ×70um2and consumes 231nW of power, which facilitates it's implementation for large chemical sensing arrays.

This paper explores the potential of partitioning the dynamic programming algorithm to utilise the capabilities of FPGA platforms for parallel genome sequence comparison and assembly. We use this to solve the prefix-suffix approximate matching problem to find overlaps between DNA strands in a given sequence. This is achieved by partitioning the basic dynamic programming (DP) algorithm into a series of discrete sub-DP calculations. Analysis of the error rate as a result of this partitioning by applying random sequences as input data is shown, and simulation results confirm good matching with the original algorithm with an error of less that 1.5% in the worst case. Optimisation for array implementation in FPGA is shown and linear scalability for larger arrays is proven. Simulation results of the whole system confirm 98.8% similarity of the overlap adjacent matrix between error and error-free data.

This paper introduces a CMOS based system that has been designed to allow parallel comparison of fragmented DNA sequences for on-chip assembly. The compatibility of different existing PC-based algorithms for implementation in CMOS is compared and the overlap-layout-consensus approach is found to be the most suitable one. The designed system comprises a scalable processing array capable of parallel computation, which allows identification of overlaps in DNA fragments in addition to error tolerance through dynamic programming. Analysis shows that there is a “pixel area vs computation time” trade-off when implementing such a parallel architecture. Results from a hypothetical assembly confirm good overlap detection and error tolerance, with up to 94% similarity in the detected overlaps, when the error is as much as 10%.

In this paper, we present a novel, ultra-long-time-constant analogue integrator for a PID controller in Lab-on-Chip (LOC) applications. A time constant of up to 5 seconds is achievable using a capacitance of only 18pF by exploiting transconductance reduction techniques involving current splitting and gm-attenuated OTA. Additionally, this architecture provides the ability to digitally tune the time constant from 200ms to 5s with 4-bit programmability. The design achieves a temperature dependance of 1.2% over the range from 0°C to 100°C with micropower consumption.