A global circuit structure is established from the circuit net-list based on knowledge about CMOS circuits. This approach first partitions the circuit network and then assigns signal flow directions accordingly. The information obtained is absent in the net-list but explicitly present in schematic diagrams. Such interpretation of a circuit network can provide extra heuristics to assist in various CMOS circuit design tasks.

A new approach utilizing MOS circuit structures extracted from a circuit net-list for designing VLSI leaf cells is described. A circuit structure is explicitly present in a circuit schematic diagram on which a designer relies for drawing a layout. However, it is absent in the net-list input to an automatic layout system. In this paper, how to extract schematic like information from a net-list and how to apply it for automatic leaf cell design are discussed.

This paper describes an approach to symbolic transistor placement from a CMOS circuit net-list as part of an automatic custom cell layout system, PLAY. It consists of two parts, extraction and refinement. The extraction process defines a set of patterns using local connection relationships. Refinement procedures assign topological attributes to each transistor through these patterns and relationships along with other heuristic knowledge. This paradigm provides a new way to embed designers' knowledge for circuit layout. Although only CMOS circuit layout placements are demonstrated, this approach can readily be extended to other technologies. Comparison between PLAY and manual design results is also reported.