We propose$\mathsf{CoHoRT}$, as the first heterogeneous cache coherent solution for mixed criticality systems (MCS) equipped with several features that targets the characteristics and requirements of such systems.$\mathsf{CoHoRT}$is requirement-aware. It provides an optimization engine to optimally configure the architecture based on system requirements.$\mathsf{CoHoRT}$is also criticality-aware. It introduces a low-cost novel architecture to enable cores to heterogeneously run different coherence protocols (time-based and MSI-based protocols). Moreover, it enables a run-time switch between these protocols to provide hardware support for mode operation switch, which is a common chal-lenge in MCS. Our evaluation shows that$\mathsf{CoHoRT}$outperforms existing solutions both from worst-case memory latency as well as overall average performance. It also illustrates that$\mathsf{CoHoRT}$is able to meet timing requirements in various MCS setups and showcases$\mathsf{CoHoRT}$'s ability to adapt to mode switches.

While data sharing is becoming a necessity in modern multi-core real-time systems, it complicates system analyzability and leads to significantly pessimistic latency bounds. This work is a step towards facilitating high-performance and coherent data sharing in real-time systems by tackling two main problems. The first is a well-acknowledged one: shared caches render cache analysis techniques useless and all cache accesses have to be assumed misses. The second is a new one, where we show that coherence interference voids classical cache analysis techniques. We contribute a solution that tackles both problems by leveraging time-based cache coherence and a novel methodology to integrate its effect into cache analysis. Thanks to this solution, we enable the usage of shared memory hierarchy with coherent shared data, while we prove that we are able to restore cache analysis; and hence, provide much tighter memory latency bounds.