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John S. J. Chen

dblp:353/7668 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › cell layout
cell layout generation		 0.011987
A Design Rule Independent Cell Compiler · DAC 1987
Electronic design automation
physical design		 0.011987
A Design Rule Independent Cell Compiler · DAC 1987
Electronic design automation › physical design
placement and routing		 0.011987
A Design Rule Independent Cell Compiler · DAC 1987
Integrated circuit design
ASIC design		 0.011987
A Design Rule Independent Cell Compiler · DAC 1987

Methods — techniques the papers use, named apart from their topics

cell synthesis algorithm · 0.0
YearPublicationVenuePosition
1987 A Design Rule Independent Cell Compiler
abstract
To achieve fast turn around, appropriate performance and efficient silicon area in ASIC design, it is desirable to have the capability of generating new customized cells overnight. A design rule independent cell compiler which is capable of generating nearly optimal layout and all the desirable user interfaces such as automatic place and route database, data sheet, SPICE information and the layout verification mode I for any user specified cell I is reported in this paper. The algorithms used for cell synthesis are also discussed in this paper.
John S. J. Chen, David Y. Chen
 DAC1