Demo Data from VLDB 2026 / reviewers in the wild / expert
Xinkai Nie
dblp:357/2710
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 56% Hardware accelerators and domain-specific architectures · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › processing-in-memory
near-memory processing |
0.7 | 1 | 2023 | TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network · DAC 2023 |
Hardware accelerators and domain-specific architectures › vision accelerator
point cloud neural network accelerator |
0.7 | 1 | 2023 | TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network · DAC 2023 |
Memory systems
processing-in-memory |
0.2 | 1 | 2023 | TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network · DAC 2023 |
Methods — techniques the papers use, named apart from their topics
tile-based processing · 0.7neighbor search · 0.7farthest point sampling · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural NetworkabstractEnergy-efficient 3D point cloud neural network accelerators are desired for autonomous driving and AR/VR applications. This paper proposes TiPU, a spatial-locality-aware near-memory tile processing unit where the point clouds are partitioned into tiles to process spatial features locally. Intra-tile farthest point sampling and cross-tile neighbor search are employed to avoid unnecessary distance computing. To efficiently facilitate the tile operations, TiPU architecture consists of a tile-based unified distance computing unit, a near-CAM feature extractor, and a near-SRAM-computing MLP engine. The experimental results show that, compared to GPU implementation, TiPU achieves 15.7× processing speed and reduces 7308× energy consumption. Jiapei Zheng, Hao Jiang 0024, Xinkai Nie, Zhangcheng Huang 0001, Chixiao Chen, Qi Liu 0010 |
DAC | 3 |