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Pixian Zhan

dblp:357/2896 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning › edge computing
edge inference
0.212023
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware · DAC 2023
Machine learning › Efficient and distributed learning
resource-constrained learning
0.212023
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware · DAC 2023

Methods — techniques the papers use, named apart from their topics

roofline model · 0.7low-voltage operation · 0.7design space exploration · 0.7
YearPublicationVenuePosition
2023 A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware
abstract
Tiny machine learning (TinyML) becomes appealing as it enables machine learning on resource-constrained devices with ultra low energy and small form factor. In this paper, a model-specific end-to-end design methodology is presented for TinyML hardware design. First, we introduce an end-to-end system evaluation method using Roofline models, which considering both AI and other general-purpose computing to guide the architecture design choices. Second, to improve the efficiency of AI computation, we develop an enhanced design space exploration framework, TinyScale, to enable optimal low-voltage operation for energy-efficient TinyML. Finally, we present a use case driven design selection method to search the optimal hardware design across a set of application use cases. Our model-specific design methodology is evaluated on both TSMC 22nm and 55nm technology for MLPerf Tiny benchmark and a keyword spotting (KWS) SoC design. With the help of our end-to-end design methodology, an optimal TinyML hardware can be automatically explored with significant energy and EDP improvements for a diverse of TinyML use cases.
Yanchi Dong, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Fengyun Yan, Yufei Ma 0002, Yun Liang 0001, Le Ye, Ru Huang 0001
DAC6