To address the control challenges of virtual coupling (VC) for heterogeneous permanent magnetic maglev trains with time-varying delays and uncertain disturbances, an observer-based distributed nonlinear consensus controller is proposed for a third-order nonlinear model. Specifically, a state observer is utilized to estimate the leader’s acceleration information, thereby reducing the communication burden. To compensate for disturbances, a fixed-time-convergence disturbance observer is proposed and theoretically demonstrated. In particular, the train-following interactions are implemented to avoid negative spacing errors as well as unreasonable acceleration and deceleration. Subsequently, the single-train and string stability are analyzed, and an upper bound on the allowed communications delay is provided. Finally, simulations demonstrate that the proposed controller exhibits strong robustness and anti-interference performance, enabling the VC to operate safely, comfortably, and reliably in the presence of communication delays and disturbances.

Finding optimal solutions for Combinatorial Optimization (CO) problems is challenging. Compared to power-hungry cryogenic quantum computer and time-consuming classical computer, quantum-inspired Ising machine solves CO problems at room temperature with fast optimization speed, low power consumption, and low cost. Nevertheless, the Ising machine still faces several challenges: digital CMOS Ising machines increase interaction freedom at the cost of greater area and larger processing time; in analog Ising machine, oscillator spins find it hard to differentiate spin states without the assistance of the post-processing algorithm, and latch spins suffer from mismatches. To address these issues, we propose an oscillator-based 3-D CMOS Analog Ising Machine (CAIM) which adopts the 12-way toroidal Hexagonal Close Packed (HCP) structure, Supply-And-Bulk Injection Locking (SABIL), and dual-mode tunable coupler. The toroidal HCP structure exhibits >2 & times; interactions compared to conventional 3-D Ising machine, while SABIL and dual-mode tunable coupler settle oscillators to a bistable ground state 2.2 & times; quicker with an 8.5 & times; wider lock range (within 5 cycles). The proposed CAIM successfully solves 3-D max-cut problems and achieves a normalized Hamiltonian energy of more than 0.98 with a maximum perfect accuracy prevalence (PAP) of 91.67%. Measurement results on a sample random Max-Cut instance demonstrate that CAIM converges to within 1.7% of the reference optimum in 5 cycles.

A high-speed train (HST) is a physically interconnected underactuated system consisting of both motor cars and trailer cars. During operation, all cars experience varying degrees of aerodynamic resistance, which imparts nonlinear characteristics to each car, posing significant challenges for controller design and stability analysis. Investigating the distributed tracking control problem for underactuated HSTs, where aerodynamic resistance acts on every car, remains a long-standing open problem. The challenge is further compounded when actuator faults are involved. Additionally, accurately obtaining the system parameters for a HST is difficult. To address these challenges, we propose a distributed tracking control approach that does not rely on system parameters, where each motor car uses only its own information, as well as that of the cars in front and behind. In this paper, a new Lyapunov function is innovatively established by incorporating elastic potential energy and relative kinetic energy into its construction. Based on this function, it is rigorously proved that the closed-loop tracking error system remains stable as long as at least one motor car exists, and that the velocity-tracking errors of the motor cars are guaranteed to asymptotically converge to zero. Furthermore, an innovative algorithm is proposed, which effectively reduces the cumulative position-tracking error by adjusting the desired trajectory. Compared with the existing results, the proposed method does not depend on any system parameters, and the resulting closed-loop tracking error system is guaranteed to be stable. Finally, we provide simulations on two HSTs to verify our theoretical results.

In this study, a novel data-driven discrete-time sliding mode control (DSMC) approach is designed for an electric multiple unit (EMU) velocity tracking control system. First, the input/output (I/O) data of the EMU are equivalently modeled as a full-format dynamic linearized (FFDL) data model to facilitate the generation of a data-driven control scheme. Subsequently, a discrete terminal sliding mode function and a new hyperbolic reaching-law are introduced to simultaneously achieve fast convergence and alleviate chattering. Based on the designed sliding mode function and reaching-law, an improved discrete-time terminal sliding mode control (iDTSMC) approach is derived using the FFDL model. The proposed approach considers the error feedback, parameter estimation errors, and total uncertainties for compensation, to achieve better control performance. The key advantages of this approach include its sole utilization of input-output data from the EMU system, low controller order, robust parameter adaptability, and anti-interference capabilities. After providing the stability analysis of the proposed method, the iDTSMC scheme is compared and tested on a simulated CRH380A high-speed train experimental platform in a laboratory. The simulation results show that the velocity tracking errors of each power unit of the EMU under the proposed control scheme are within$-$0.112 km/h, 0.118 km/h, and the control forces and accelerations are within$-$51 kN, 43 kN and$-$0.952 m/s$^2$, 0.827 m/s$^2$, respectively, with stable fluctuations. Comparative experimental results demonstrate the effectiveness and superiority of the proposed strategy, which remains robust in the presence of disturbances.Note to Practitioners—This study is inspired by the problem of EMU operation control, however, it is also applicable to other systems with trajectory tracking characteristics. Existing automatic train driving control methods are usually based on a dynamics model of the train, which is easily affected by the external environment. In this study, a new data-driven control method is proposed. A discrete terminal sliding mode control function and a new hyperbolic reaching-law were designed based on a dynamic linearized data model equivalent to the EMU operation process. In contrast to similar existing works, the control scheme does not require an accurate EMU dynamic model and is easy to implement. Preliminary simulation experiments show that the method is feasible, however, it has not been incorporated into the train’s physical system, nor has it been tested in production. In future research, we plan to promote a combination of control theory and manufacturing practices.

A novel MIMO data-driven integral predictive sliding mode control (DIPSMC) scheme is proposed based on the dynamic linearization (DL) and state observer method, intended for the automatic driving systems of multi-power unit high-speed trains (HSTs) influenced by system couplings, input constraints, and external disturbances. Initially, by introducing a nonlinear fast integral terminal sliding mode (NFITSM) surface instead of the traditional sliding mode function, facilitating rapid convergence of system errors and reducing sliding mode chattering. Additionally, a parameter update law and an adaptive extended state observer (AESO) are designed to estimate input gains and total uncertainties, respectively, addressing the issue in traditional discrete-time sliding mode control (DSMC) that requires large switching gains to handle disturbances. Subsequently, combining the rolling time domain optimization concepts in predictive control, it follows the reference trajectory of the predefined reaching law, allowing the system to explicitly handle control constraints and obtain higher tracking accuracy. This scheme concurrently accounts for and compensates the total uncertainties arising from system couplings, parameter estimation errors, and unknown disturbances. The principal advantage of this scheme is its design based entirely on a DL data model equivalent to the HST system, characterized by a low-order controller with robust chattering mitigation and disturbance rejection capabilities. Finally, comparative testing experiments of the proposed scheme are conducted on the CRH380A HST simulation platform. Experimental results indicate that under the proposed control scheme, the velocity and displacement error ranges for each power unit of the HST are within ±0.156 km/h and$\pm 1.~1$m, respectively, with control force and acceleration ranges of [−53.2 kN, 46.5 kN] and [−0.568 m/s2, 0.476 m/s2], respectively, and low chattering levels, fulfilling the efficiency and safety requirements of the trains.

Providing personalized and timely feedback for student's programming assignments is useful for programming education. Automated program repair (APR) techniques have been used to fix the bugs in programming assignments, where the Large Language Models (LLMs) based approaches have shown promising results. Given the growing complexity of identifying and fixing bugs in advanced programming assignments, current fine-tuning strategies for APR are inadequate in guiding the LLM to identify bugs and make accurate edits during the generative repair process. Furthermore, the autoregressive decoding approach employed by the LLM could potentially impede the efficiency of the repair, thereby hindering the ability to provide timely feedback. To tackle these challenges, we propose FastFixer, an efficient and effective approach for programming assignment repair. To assist the LLM in accurately identifying and repairing bugs, we first propose a novel repair-oriented fine-tuning strategy, aiming to enhance the LLM's attention towards learning how to generate the necessary patch and its associated context. Furthermore, to speed up the patch generation, we propose an inference acceleration approach that is specifically tailored for the program repair task. The evaluation results demonstrate that FastFixer obtains an overall improvement of 20.46% in assignment fixing when compared to the state-of-the-art baseline. Considering the repair efficiency, FastFixer achieves a remarkable inference speedup of 16.67× compared to the autoregressive decoding algorithm.

The V2V (vehicle-to-vehicle) energy swapping strategy provides an alternative charging for electric vehicles (EVs) to alleviate the problem of overload caused by the un-coordinately charges in residential microgrids (MGs) during the peak. However, stochastic factors of EVs and neglected network losses cause inflexibility and impracticality of the existing methods. Focused on the stochastic factors of energy trading caused by EVs and network constraints in residential MGs scenario, a V2V Energy Trading in Residential Microgrids (VETRM) considering multiple constraints via Bayesian game model is proposed. Frist, the Bayesian game modeled types of players by information including the stochastic characteristics of EVs, which results in uncertainties that the game participants determine the roles of seller or buyer that depends on the states of power surplus or lack. Then, utility functions based on the sensitivity analysis to the impact of V2V transactions on the network and to guarantee the exchange of energies to inviolate network constraints are established. The solution of model based on game equilibrium has been rigorously derived. Two scenarios fulfill the comparisons of existing models and proposed model for simulation including IEEE 33 and IEEE 123 bus system that the proposed model improve the revenues of EV in reducing energy loss and smoothing the peak of the power system to demonstrate the effectiveness of the VETRM model.

Recently, the graphics processing unit (GPU) has made significant progress as a general-purpose parallel processor. The CPU and GPU cooperate together to solve data-parallel and control-intensive real-world applications in an optimized fashion. For example, emerging heterogeneous computing architectures such as Intel Sandy Bridge and AMD Fusion integrate the functionality of the CPU and GPU in a single die. However, the single-die CPU-GPU heterogeneous computing architecture faces the challenge of tight budget of die area. The conventional homogenous interconnect fails to provide satisfactory performance by fully exploiting the given area budget in the heterogeneous processing era. In this article, we aim to implement an interconnect network within an area budget for a CPU-GPU heterogeneous computing architecture. We propose iConn, a 2D mesh-style on-chip heterogeneous communication infrastructure. In iConn, a set of GPU logical units such as the stream processors, the texture units, and the rendering output units form a computing unit (CU). Differing from conventional homogenous router design, iConn adopts nonuniform on-chip routers in order to meet the unique communication demands from each single CPU and CU. The routers can also dynamically allocate their buffers across all virtual channels (VCs) to meet the latency requirements of CPUs and CUs. Moreover, the memory controller scheduling algorithm is modified from traditional load-over-store scheduling in order to prioritize the traffic. Our simulation results show that iConn improves the performance of CPUs by 23.0% and CUs by 9.4%.

With silicon optical technology moving toward maturity, the use of photonic networks-on-chip (NoCs) for global chip communication is emerging as a promising solution to the communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ambient temperature variations because their basic constituents, ring resonators, are themselves sensitive to those variations. Since ring resonators are basic building blocks for photonic modulators, switches, multiplexers, and demultiplexers, variations of on-chip temperature pose serious challenges to the proper operation of photonic NoCs. Proposed methods that mitigate the effects of temperature at the device level are either difficult to use in CMOS processes or not suitable for large scale implementation. In this paper, we propose Aurora, a thermally resilient photonic NoC architecture design that supports reliable and low bit error rate (BER) on-chip communications in the presence of large temperature variations. Our proposed architecture leverages cross-layer solutions at the device, architecture, and operating system (OS) layers that individually provide considerable improvements and synergistically provide even more significant improvements. To compensate for small temperature variations, our design varies the bias current through ring resonators. For larger temperature variations, we propose architecture-level techniques to reroute messages away from hot regions, and through cooler regions, to their destinations. We also propose a thermal/congestion-aware coscheduling algorithm at the OS level to further lower BER by reorganizing the thermal profile of the chip. Our simulation results show that Aurora provides a robust architectural solution to handle temperature variation effects on future photonic NoCs. For instance, average BER and message error rate are reduced by 96% and 85%, respectively, when the combined thermal optimization scheme [shortest path first+ OS] is applied. From the perspective of power efficiency, Aurora is also superior to conventional photonic NoC architectures by as much as 37%.

Phase change memory is emerging as a promising candidate for building up future energy efficient memory systems. To achieve high-performance and energy proportional design, phase change memory devices need to be reorganized so that (1) the relatively long latency of phase change memory devices should be hidden; (2) unnecessary power waste of phase change memory need to be preserved. Previous studies show that conventional memory ranks could be broken down into multiple smaller ranks for increased concurrency and lower power consumption. Nevertheless, the conventional electrical bus is incapable of supporting a large number of memory chips due to its insufficient load capacity and signal traversing speed. In this paper, we propose a phase change memory system design that leverages the state-of-art photonic links to overcome this issue. Moreover, thanks to the flexibility of photonic links, it is possible to amortize the small-rank penalty (e.g. the rank-to-rank switch overhead) by partitioning the channels either statically or dynamically. Our experimental results show that photonically interconnected phase change memory can increase the system performance (IPC) by up to 19% while saving 35% memory system power.

Photonic Network-on-Chips (NoCs) have recently been proposed due to their inherent low latency and high bandwidth. However, the high static power of the photonic components (e.g. laser source, resonators and waveguides) often results in energy-inefficient architectures. In this paper, we advocate the Energy-Star Photonic Network (ESPN) architecture that optimizes energy utilization via a two-pronged approach: (1) by enabling dynamic resource provisioning, ESPN adapts photonic network resources based on runtime traffic characteristics and (2) by utilizing all-optical adaptive routing, ESPN improves energy efficiency by intelligently exploiting existing network resources without introducing high latency and power hungry auxiliary routing mechanisms. Our evaluation results show that compared to the baseline design, ESPN reduces power and energy consumption under synthetic traffic patterns by 50% and 58% respectively.

As high-performance computing device, the GPU has exposed bandwidth and latency bottlenecks in on-chip interconnect and off-chip memory access. To eliminate such bottlenecks, we employ silicon nanophotonics and 3D stacking technologies in GPU microarchitecture. This provides higher communication bandwidth and lower latency signaling mechanisms at reduced power. Furthermore, to insulate the performance of the GPU compute cores from the interconnect bottlenecks we propose a novel interconnect aware thread scheduling scheme to alleviate the traffic congestion. We evaluate a 3D stacked GPU with 2048 SIMD cores having photonic interconnect. The photonic multiple-write-single-read crossbar network with 32B channel bandwidth on average, achieves 96% power reduction. We anticipate that for emerging workloads and microarchitectures the implications of the proposed ideas are far reaching in terms of power and performance.

With silicon optical technology moving towards maturity, the use of photonic network-on-chip (NoCs) for global chip communication is emerging as a promising solution to communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ambient temperature variations because their basic constituents, ring resonators, are themselves sensitive to those variations. Since ring resonators are basic building blocks for photonic modulators, switches, multiplexers, and demultiplexers, variations of on-chip temperature pose serious challenges to the proper operation of photonic NoCs. Proposed methods that mitigate the effects of temperature at device level are either difficult to use in CMOS processes or not suitable for large scale implementation. In this paper, we propose Aurora, a thermally resilient photonic NoC architecture design that supports reliable and low bit error rate (BER) on-chip communications in the presence of large temperature variations. Our proposed architecture leverages solutions at both device and architecture layers that synergistically provide significant improvements. To compensate for small temperature variations, our design varies the bias current through ring resonators. For larger temperature variations, we propose architecture-level techniques to re-route messages away from hot regions, and through cooler regions, to their destinations, thereby lowering BER. Our simulation results show that Aurora provides a robust architectural solution to handle temperature variation effects on future photonic NoCs. For instance, average BER and message error rate (MER) are reduced by 78% and 30% respectively when the combined device and architectural technique (SPF) is applied. From the perspective of power efficiency, Aurora is also superior to conventional photonic NoC architectures by as much as 33%.

The goal of this paper is to develop a neural network-based scheme for fault detection and isolation in reaction wheels (actuators) of a satellite. To achieve this objective, three neural networks are developed for modeling the dynamics of a reaction wheel on all the three axes separately. A recurrent neural network with backpropagation training algorithm is considered for representing the highly nonlinear dynamics of the actuator. The capabilities and potential of the proposed neural network-based fault detection and isolation (FDI) methodology is investigated and a comparative study is conducted with the performance of a generalized Luenberger observer-based scheme. Simulation results demonstrate clearly the advantages of our proposed neural network scheme studied in this paper.

The objective of this paper is to develop a dynamic neural network scheme for fault detection and isolation (FDI) in the reaction wheels of a satellite. Specifically, the goal is to decide whether a bus voltage fault, a current loss fault or a temperature fault has occurred in one of the three reaction wheels and further to localize which wheel is faulty. In order to achieve these objectives, three dynamic neural networks are introduced to model the dynamics of the wheels on all three axes independently. Due to the dynamic property of the wheel, the architecture utilized is the Elman recurrent network with backpropagation learning algorithm. The effectiveness of this neural network-based FDI scheme is investigated and a comparative study is conducted with the performance of a generalized observer-based scheme. The simulation results have demonstrated the advantages of the neural network-based method proposed.