Diffusion models have become essential for high-fidelity 3D MRI synthesis, yet their deployment remains constrained by substantial GPU resource demands arising from hundreds of U-Net evaluations per sample and a highly heterogeneous kernel behavior. This paper performs a comprehensive performance analysis of the state-of-the-art medical diffusion model, Med-DDPM, across three generations of NVIDIA architectures to study kernel-level runtime breakdowns, instruction-mix characteristics, memory system utilization, warp-level activities, and profiler priority-score estimates. We show that training is overwhelmingly dominated by cuDNN convolution and implicit-GEMM kernels, with inefficiencies arising from memory-access patterns, tensor-layout conversions, and limited Tensor Core utilization. Guided by these insights, we evaluate two architecture-aware optimizations TF32 Tensor Core activation and a 3D channels-last layout and demonstrate that they reduce SM cycles by up to 100x, cut dynamic instructions by 100x, raise Tensor Core utilization from 1.45 to 9.98x, and increase IPC by 7% on A100, all without degrading synthesis quality.

As various types of applications are released; it is required to have more adequate cache replacement policy in the cache of microprocessors. Based on our investigation, cache line eviction is not determined by only a single factor, so multiple factors should be evaluated to find optimal answers. The Least Recently Used (LRU) can only exploit data that has a short reuse distance. However, we observe some of the applications have long reuse distances and some others have a mix of short, mid, and long reuse distances. If the replacement policy can learn the access pattern, we could get better cache performance with extra storage for training and driving the cache. In this paper, we proposed a policy that will train periodically to understand the reuse pattern of the trace and determine the capped reuse distance that will be used for ceiling partial ways of the LLC (Last Level Cache). We see that LRU covers 100% of the short reuse distance but only 3% mid-range and 0% long-range reuse distances. Whereas Ship++ covers 87% short, 67% mid, 46% long distances and Hawkeye covers 94% short, 60% mid, 35% short, similarly our proposed Trace characterization based capped reuse history (TCRH) covers 98% short, 55% mid, 31% long distances. The main goal of the proposed scheme is that the replacement policy should work adequately in different patterns of trace that can be a short-reuse distance, long reuse distance, or mixed reuse distance. We capture some key parameters of the trace by training. Overall TCRH improves MPKI over LRU by ~12% which is 12% more than Hawkeye and 30% more than Ship++.

Hardware-based malware detection is becoming increasingly important as software-based solutions can be easily compromised by attackers. Many of the existing hardware solutions are based on statistical learning blocks with processor behavioral information, which can be captured from the PMC (performance monitoring counters). The performance of the learning techniques relies primarily on the quality of data. However, due to the limited number of PMCs in a processor, only a few behavioral events can be monitored simultaneously. In this paper, we focus on multiple steps to investigate critical issues of PMC based malware detection: (i) statistical characterization of malware; (ii) distribution-based feature selection; (iii) trade-off analysis of complexity and accuracy; and (iv) design alternatives for PMC-based malware detection. Our experimental results show that the proposed detection scheme can provide highly accurate malware detection. As architectural implications, hardware acceleration as well as additional PMC registers are discussed for more accurate malware detection in real-time.

Due to the limited number of performance counters, the selection of architectural features is a critical issue to provide high quality data for malware detection. To address the issue, we come up with a metric called Degree of Distribution (DoD) as one of the malware detection criteria. Our experimental results show that the DoD can differentiate malware applications from benign applications and provide highly accurate detection through the machine learning framework. As architectural implications, hardware acceleration as well as additional PMC registers are discussed for more accurate malware detection in real-time.

Advances in process technology has enabled the integration of many cores on a single die. The advent of many core systems has led to a commensurate increase in cache coherence complexity. As a solution to this problem, researches have proposed directory based protocols, which are scalable alternatives to snoop-based protocols. Although write-invalidation based directory protocols enhance the performance of large-scale multiprocessors, coherence misses are intrinsic impediments in such systems. Write-update protocols were proposed as a means to reduce these coherence misses. However, previous researches have shown that pure write-update protocol is highly undesirable because of the heavy traffic caused by the aggressive updates. In order to remedy these limitations, we propose a performance-aware mechanism which dynamically classifies the sharers of each cache block, either as a weak-sharing-group or an efficient-sharing-group and exploit this dynamic classification as a metric for seamless dynamic adaptation between write-invalidate and write-update strategy on a per block basis. Exploitation of the dynamic adaptation of the protocol, based on the sharing-group speculation, reduces unnecessary accesses to the shared last level cache and hence reduces the traffic caused by coherence misses and directory accesses. Simulation results on a 64-core CMP show that our proposed method can achieve 15 % (average) speedup over the baseline directory-based MOESI cache coherence protocol with PARSEC workloads. Our proposed work also reduces the L1 cache miss rate by 17 %(average). The network traffic caused by directory accesses and L1 read misses are also reduced by 16% and 17% respectively.

The goal of this research is to design a low cost cache replacement algorithm that achieves comparable performance to existing scheme. In previous work, we proposed an enhancement to the SLRU (Segmented LRU) algorithm called fixed SLRU that fixes the number of protected and probationary segments. Due to an ineffective simulation environment, we were unable to fully understand our results. In this work, we will test fixed SLRU with an improved simulation environment, and propose three enhancements to the algorithm: cache bypassing, random promotion, and aging. Our experiment results show that fixed SLRU achieved an average speed up of 7.00% over LRU, and 4.22% over SLRU, with a maximum speed up of 43.55% over LRU, and 41.59% over standard SLRU. With certain enhancements applied, we achieved a maximum speed up of 61.70% over LRU.

In computer design area, pre-silicon early-stage design exploration requires the detailed simulation which is running applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite takes several weeks to several months. Among many techniques for reducing simulation time, a tool called SimPoint is popularly used. Even though, simulation load with the reduced workloads by SimPoint is still heavy considering design complexity of modern microprocessors. Basic motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would eliminate those simulation points from the simulation setup procedure. In this paper, we focus on identifying those simulation points which have high sensitivity or low sensitivity, by which overall simulation methodology can be effectively improved. We also performed the performance-sensitivity-based similarity analysis for workload reduction by using statistical technique. Our experiment results show that the proposed scheme provides around 50% reduction with 0.2%-3.5% error rate over original SimPoint method.

Cache replacement policies are an essential part of the memory hierarchy used to bridge the gap in speed between CPU and memory. Most of the cache replacement algorithms that can perform significantly better than LRU (Least Recently Used) replacement policy come at the cost of large hardware requirements [1][3]. With the rise of mobile computing and system-on-chip technology, these hardware costs are not acceptable. The goal of this research is to design a low cost cache replacement algorithm that achieves comparable performance to existing scheme. In this paper, we propose two enhancements to the SLRU (Segmented LRU) algorithm: (i) fixing the number of protected and probationary segments based on effective segmentation ratio with increasing the protected segments, and (ii) implementing selective caching, to achieve more effective eviction, based on preventing dead blocks from entering the cache. Our experiment results show that we achieve a speed up to 14.0% over LRU and up to 12.5% over standard SLRU.

Programming for CUDA devices presents the paradigm of warp-synchronous nature. This paper covers an implementation of an AES decryption kernel that makes use of warp-synchronicity. The operation of the various types of memories found in a CUDA device also required some analysis for a warp-synchronous implementation. The CUDA based implementation of AES256 was tested on several CUDA devices of various compute capabilities against the original single-threaded CPU implementation on various machines using encrypted messages of sizes ranging from 2MiB to 1GiB. The time taken for the GPUs to decrypt a message has varied between GPU architectures, with some achieving a 6x speedup.

Dynamic programming matrices and the P7Viterbi algorithm of HMMER 3.0 show high parallelism in its code. Within the code, every query can have its score calculated in parallel with one thread per query. In this paper, these parallel features were exploited through the use of CUDA and a GPGPU. The CUDA implementation of this algorithm being performed on the Tesla C1060 enabled a 10-15x speedup depending on the number of queries. Without concurrent kernel execution and memory transfers a speedup of over 4x was achieved in terms of the total execution time. With a wide range of data sizes where the CPU has greater performance, it would be important that CUDA enabled programs properly select when to and not utilize the GPU for acceleration.

Multi-core trends are becoming dominant, creating sophisticated and complicated cache structures. Also, the bigger shared level-2 (L2) caches are demanded for higher cache performance. One of the easiest ways to design cache memory for increased performance is to double the cache size. However, the big cache size is directly related to the area and power consumption. Especially in mobile processors, simple increase of the cache size may significantly affect its chip area and power. In this paper, we propose a composite cache mechanism for L2 cache to maximize cache performance within a given cache size. This technique can be used without increasing cache size and set associativity by emphasizing primary way utilization and pseudo-associativity. Based on our experiments with the sampled SPEC CPU2000 workload, the proposed cache mechanism shows the remarkable reduction in cache misses. The variation of performance improvement depends on cache size and set associativity, but the proposed scheme shows more sensitivity to cache size increase than set associativity increase.

As the network environment is rapidly changing, network interfaces demand highly intelligent traffic management (on control plane) in addition to the basic requirement of wire speed packet forwarding (on data plane). Several vendors are releasing various network processors (NPS) in order to handle these demands, but they are optimized for throughputs mostly in data plane. As demands for control plane applications (e.g., quality of service) grow, efficient control plane processing will become increasingly important to good performance of network interface. In this paper, we explore acceleration techniques to improve the performance of control plane network applications. Three applications including media transcoding and transaction applications are analyzed in detail. The result of workload characterization shows that wide-issue configuration shows early saturation in performance, and there is no common bottleneck among applications based on sensitivity analysis. Therefore, we study to get each application have its own hardware acceleration module in order to accomplish the required throughput on OC-768 or higher. Our approach includes array style accelerator for media transcoding applications and partitioned lookup mechanism for lookup-table-related applications. Performance analysis of the proposed techniques shows significant improvement over the baseline configuration. Such hardware accelerators provide large packet-level parallelism proportional to the number of processing elements added. Our analyses of the proposed techniques suggest future directions for the design of high-performance NPs.

Complex network protocols and various network services require significant processing capability for modern network applications. One of the important features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applications-scheduling and queue management algorithms, and we propose application-specific acceleration techniques that use instruction-level parallelism (ILP) and packet-level parallelism (PLP) in these applications. From the PLP perspective, we propose a hardware acceleration model based on detailed analysis of congestion control applications. In order to get large throughputs, a large number of processing elements (PEs) and a parallel comparator are designed. Such hardware accelerators provide large parallelism proportional to the number of processing elements added. A 32-PE enhancement yields 24/spl times/ speedup for weighted fair queueing (WFQ) and 27/spl times/ speedup for random early detection (RED). For ILP, new instruction set extensions for fast conditional operations are applied for congestion control applications. Based on our experiments, proposed architectural extensions show 10%-12% improvement in performance for instruction set enhancements. As the performance of general-purpose processors rapidly increases, defining architectural extensions (e.g., multi-media extensions (MMX) as in multimedia applications) for general-purpose processors could be an alternative solution for a wide range of network applications.

Complex network protocols and various network services require significant processing capability for modern intelligent network applications. One of the significant features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applications - scheduling and queue management algorithms, and we propose application-specific acceleration technique using ILP (instruction level parallelism) and PLP (packet level parallelism). From the ILP perspective, new instruction set extensions for fast conditional operations are applied for congestion control applications. Based on our experiments, proposed architectural extensions show 10-12% improvement in performance for instruction set enhancements. For PLP, we propose a hardware acceleration model based on detailed analysis of congestion control applications. In order to get large throughputs, large number of processing elements and a parallel comparator are designed. Such hardware accelerators provide large parallelism proportional to the number of processing elements added. As the performance of general purpose processors rapidly increases, defining architectural extensions (e.g., MMX as in multimedia applications) for general purpose processors could be an alternative solution for wide range of network applications.

Compression and encryption applications are important components of modern multimedia workloads. These workloads are typically executed on application specific integrated circuits (ASICs), application specific processors (ASPs), or general purpose processors (GPPs). GPPs are flexible and allow changes in the applications and algorithms better than ASICs and ASPs. However, executing these applications on GPPs is done at a high cost. In this paper, we analyze media compression and encryption applications from the perspective of executing them on a programmable general purpose processor versus ASPs. We select 12 programs from various types of compression and encryption applications. The instruction mix, data types of memory operations, and memory access workloads during the execution of these programs are analyzed. Most of these applications involve processing the data through execution phases (e.g., quantization, encoding, etc.) and temporary results are stored and retrieved between these phases. A metric called overhead memory-access bandwidth per input and output byte is defined to characterize the temporary storage and retrieval of data during execution. We observe that more than 90 percent of the memory accesses made by these programs are temporary data stores and loads arising from the general purpose nature of the execution platform. We also verify the robustness of the proposed metric on different experimental environments using various input data properties and compiler optimizations.

Modern network interfaces demand highly intelligent traffic management in addition to the basic requirement of wire speed packet forwarding. Several vendors are releasing network processors in order to handle these demands. Network workloads can be classified into data plane and control plane workloads, however most network processors are optimized for data plane. Also, existing benchmark suites for network processors primarily contain data plane workloads, which perform packet processing for a forwarding function. We present a set of benchmarks, called NpBench, targeted towards control plane (e.g., traffic management, quality of service, etc.) as well as data plane workloads. The characteristics of NpBench workloads, such as instruction mix, parallelism, cache behavior and required processing capability per packet, are presented and compared with CommBench, an existing network processor benchmark suite [T. Wolf et. al., (2000)]. We also discuss the architectural characteristics of the benchmarks having control plane functions, their implications to designing network processors and the significance of instruction level parallelism (ILP) in network processors.

With the growth of the Internet and mobile communication industry, multimedia applications form a dominant computer workload. Media workloads are typically executed on Application Specific Integrated Circuits (ASICs), application specific processors (ASPs) or general purpose processors (GPPs). GPPs are flexible and allow changes in the applications and algorithms better than ASICs and ASPs. However, executing these applications on GPPs is done at a high cost. In this paper, we analyze media compression/decompression algorithms from the perspective of the overhead of executing them on a programmable general purpose processor versus ASPs. We choose nine encode/decode programs from audio, image/video and encryption applications. The instruction mix, memory access and parallelism aspects during the execution of these programs are analyzed. Memory access latency is observed to be the main factor influencing the execution time on general purpose processors. Most of these compression/decompression algorithms involve processing the data through execution phases (e.g. quantization, encoding, etc) and temporary results are stored and retrieved between these phases. A metric called overhead memory-access bandwidth per input/output byte is defined to characterize the temporary memory activity of each application. We observe that more than 90% of the memory accesses made by these programs are temporary data stores and loads arising from the general purpose nature of the execution platform. We also study the data parallelism in these applications, indicating the ability of instruction level and data level parallel processors to exploit the parallelism in these applications. The parallelism ranges from 6 to 529 in encode processes and 18 to 558 in decode processes.