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Greg Chrysler

dblp:36/1874 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Energy-efficient computing · 55% Processor architecture and microarchitecture · 45%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing
thermal management
0.112006
Cooling a Microprocessor Chip · Proc. IEEE 2006
Processor architecture and microarchitecture
microprocessor design
0.012006
Cooling a Microprocessor Chip · Proc. IEEE 2006
Energy-efficient computing
power density
0.012006
Cooling a Microprocessor Chip · Proc. IEEE 2006

Methods — techniques the papers use, named apart from their topics

thermal modeling · 0.1packaging design · 0.1transistor sizing · 0.0supply voltage selection · 0.0body bias · 0.0
YearPublicationVenuePosition
2009 Dynamic thermal management using thin-film thermoelectric cooling
abstract
Multi-core architectures require Dynamic Thermal Management mechanisms (DTM) to handle (1) multiple hotspots and (2) global chip heating effect while finding the best trade-off between performance and thermal control. In that scenario Thin-Film Thermoelectric Cooling devices can be used to mitigate both effects since they provide on-die localized cooling with a dynamic and heterogeneous effect. This work proposes controlling TFTECs from the microarchitecture for an enhanced Dynamic Thermal Management in multi-core architectures. We show that by using our TFTEC-based proposals the performance is within 8% of that of a thermally-unconstrained processor.
Pedro Chaparro, José González 0002, Qiong Cai, Greg Chrysler
ISLPED4
2006 Cooling a Microprocessor Chip
abstract
Increasing microprocessor performance has historically been accompanied by increasing power and increasing on-chip power density, both of which present a cooling challenge. In this paper, the historical evolution of power is traced and the impact of power and power density on thermal solution designs is summarized. Industrial and academic researchers have correspondingly increased their focus on elucidating the problem and developing innovative solutions in devices, circuits, architectures, packaging and system level heatsinking. Examples of some of the current packaging and system thermal solutions are provided to illustrate the strategies used in their design. This is followed by a brief discussion of some of the future trends in demand and solution strategies that are being developed by academic and industrial researchers to meet these demands. Potential opportunities and limitations with these strategies are reviewed.
Ravi Mahajan, Chia-Pin Chiu, Greg Chrysler
Proc. IEEE3
2004 Design optimizations for microprocessors at low temperature
abstract
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30 of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.
Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
DAC7