Level shifter and floating power supply for high-side channel are major challenges in high-voltage high-frequency DC-DC converters. This paper presents an up to 10 MHz GaN driver suitable for high-power-density automotive electronics. An adaptive short-pulse (ASP) high d$V_{\text {sw}}$/d$t$noise immunity level shifter (LS) with efficient analog noise blanker (ANB) is proposed, achieving 6.8 ns minimum on-time at 10 MHz$f_{\text {sw}}$. A dual-MOS-switches bootstrap (DMSB) circuit is proposed to ensure that the bootstrap (BST) rail achieves saturation (>80%) at 10 MHz frequency by sensing$V_{\text {sw}}$and the low-side gate drive signal. To validate this work, a half-bridge GaN driver has been fabricated in a$0.5~\mu $m 80 V HV CMOS process and the active area is$1.44\times 1.42$mm2. The d$V$/d$t$immunity has been verified both in Buck converter and double pulse conditions, which is up to 46 V/ns at 60V Buck converter and 56 V/ns at 48 V double pulse topology. The proposed DMSB technique achieves a peak efficiency of 86.7% at 10 MHz for 12-to-5V conversion, representing a 6.7% improvement over the conventional approach.

Insulated gate bipolar transistors (IGBTs) are the key component in power electronics, and the intricate relationship between their performance and structural parameters poses a formidable challenge in the design process. This article proposes an automatic optimal design method for IGBT structural parameters to leverage the pretrained machine learning (ML) model to efficiently predict the initial IGBT device’s performance, followed by utilizing the differential evolution (DE) algorithm to automatically adjust structural parameters based on the disparity between predicted and expected device performance until the expected performance is achieved. The method is validated in the design of punch-through IGBTs (PT-IGBTs) and trench gate field-stop IGBTs (FS-IGBTs), and the performance of technology computer-aided design (TCAD) simulation of the designed device is similar to the target performance. In particular, the simulation results of the designed FS-IGBT are highly fitted to the datasheet of the commercial device, which verifies the generalizability and effectiveness of the method. In addition, comparative analyses with various algorithms show DE provides the fastest optimization and extraordinary robustness under the exact specifications. Crucially, the proposed design scheme aligns with semiconductor physics. The method simplifies IGBT design without the need for manual tuning and TCAD tool simulation.

A fully-integrated half-bridge driver with dual N-type power transistors is proposed in this paper, which adopts on-chip charge pumps with integrated capacitors based on charge sharing to avoid external bootstrap components. Without bootstrap-capacitor charging paths through low-side power transistors and high-frequency high-power switching nodes, overcharge and large electro-magnetic interference (EMI) can be avoided by eliminating parasitic interconnect inductance and body diode. Adaptive dead time is employed to enhance efficiency, enabling the system to achieve appropriate dead times in various applications. Besides, 100% duty-cycle control is realized by duty-cycle detection and additional continuous charge pump, which can charge the on-chip driver capacitor during on-time, the restriction of minimum off-time is eliminated and the proposed driver can work at full duty cycle range. The proposed charge-sharing-based (CSB) half-bridge driver with any duty-cycle capability embedded in a buck converter with 2A load is implemented in a 0.18 μm BCD technology, which occupies an active area of 0.151mm2. Verification results demonstrate that a 2.2 MHz switching frequency is realized with 2.4V–5.5V input voltage and a peak efficiency of 96.8% is achieved for 5 to 4V conversion. The minimum regulation voltage difference between input voltage and output voltage is 70 mV with the help of 100% duty-cycle circuit.

A voltage-controlled-oscillator(VCO)-based modulation PFM-PWM Buck converter is proposed to effectively reduce the output voltage ripple in PFM mode. The converter employs a VCO circuit instead of a hysteresis comparator to achieve PFM operation, ensuring a single inductor current pulse per cycle regardless of load current. A loop model for PFM mode is established for design of stability. Additionally, a hysteresis-based seamless mode transition method is incorporated to ensure converter consistent operating during full load range. Implemented using$0.18~\mu $m BCD technology, experimental results demonstrate minimal output voltage ripple of 2.5mV in PWM mode and of 8mV in PFM mode with empty load at output voltage of 5V. Moreover, the converter achieves optimal efficiency of up to 92%.

A current-efficient and fast-transient p-type low-dropout regulator (LDO) for high-current load transient in mobile phone applications is presented in this article. A low-power Auxiliary-Path Push-Pull (AP3) buffer is employed to provide both high charging and discharging current for gate-capacitance (CgP) of power MOS, hence the undershoot and overshoot performance are optimized simultaneously; Meanwhile the auxiliary path of the buffer further accelerates the transient response. Moreover, the shaped-hybrid-bias circuit accurately control the upper and lower limits of EA’s bias current, by this, maximum LDO’s bandwidth is well controlled and keeps proper margin to the self-resonant frequency of off-chip capacitor, which guarantees good loop stability over wide load range. This circuit has been implemented in a 0.18-µm standard 5V CMOS process and occupies a silicon area of 400 × 250 µm2, where 5V devices with a 500-nm minimum channel length are used. With a 1-µF output cap and load steps between 0 A and 270 mA, with 300ns edge time, experimental results show that it features 19/14 mV of undershoot/overshoot at load transient

In this article, a monolithic gallium nitride (GaN)-based half-bridge power stage is proposed for high frequency power converter. A level shifting technique with buffering device and shielding capacitance is designed to perform communications in half-bridge topologies with high reliability and low propagation delay. To prevent the missing pulse or output latch during deadtime, a negative voltage pull-down circuit is designed. Implemented with a$0.25\mu \mathrm{m}$15-V enhanced mode GaN (eGaN) process, this work consists of optimized delay matching, monolithic gate drivers and power high electron mobility transistors(HEMTs) as well. The implementation results show that this work can achieve a propagation delay of no more than 6.5ns, a delay mismatch within 2.5ns and a CMTI capability above 150V/ns at 30Mhz switching frequency.

A novel adaptive peak inductor current limit for double hysteresis Buck working in DCM is proposed in this paper to improve efficiency at light load. Due to constant peak inductor current limit, conduction loss of double hysteresis Buck is the main reason that impose restrictions on efficiency at light load. To overcome the problem, peak inductor current limit decrease adaptively while the load changes from heavy to light by sampling time of sleep period. Furthermore, a dynamic quiescent current control method is adopted to reduce quiescent loss of double hysteresis Buck. The propose Buck chip is fabricated in$0.18 \mu\mathrm{m}$BCD process. The experiment results show that the maximum-improvement of efficiency is 3%.

In this paper, a high-noise-immunity capacitive-coupled level shifter with digital noise blanker (DNB) is presented for GaN drivers. During and after$\text{d}V$/dt transitions, the DNB blanks the common mode noise induced by$\text{d}V$/dt and converts the differential mode noise due to mismatch effect to common mode noise. This enables high$\text{d}V$/dt immunity of 200V/ns and high mismatch tolerance not less than 15%. Moreover, a dynamic discharge control (DDC) circuit prevents coupling capacitor from charging the floating power rail within a wide negative$\text{d}V$/dt transition range and achieves fast reset for high frequency operation. High speed, low power consumption and down to −5V negative floating power rail tolerance are also achieved. The proposed level shifter is fabricated in a 0.5-$\mu \text{m}$BCD process and occupies an active chip area of 0.051mm2. Experimental results confirm that the proposed level shifter works at 50V 50MHz, achieving power consumption of 27.3pJ/transition and 1.26ns average delay with a small figure of merit (5.5(pJ$\cdot $ns)/($\mu \text{m}^{3}\cdot \text{V}$)). The effect of the DDC is confirmed within negative$\text{d}V$/dt transition range of −5V/ns$\sim -50\text{V}$/ns.

The primary-side regulation (PSR) flyback converters with the feature of constant current (CC) and constant voltage (CV) are widely used in charger systems and adaptors of electronic devices. However, the conventional method of CC control is complex and inaccuracy, and more circuits should be added to improve accuracy causing more complex design and larger cost. In this paper, a novel strategy of CC control strategy based on large signal control is proposed to achieve simple and high-precision CC control which operates seamlessly as working state switched between CC and CV. The control chip is implemented in a 0.18μm BCD process, and the deviation of output current in CC mode is less than ± 2% without loop compensation. It well meets the demand of large charging current in startup and limiting current under low voltage condition.

This paper presents an anti-overcharged high-dV/dt-immunity capacitive level shifter with dynamic discharge control (DDC) for half-bridge GaN driver. The DDC prevents overcharge of the floating power supply capacitor during high negative dV/dt transitions and is suitable for a wide variation range of negative dV/dt transitions of floating power supply. Moreover, a fault-logic blanking block is introduced to guarantee the robust of output logic during ultra-high dV/dt transitions. The proposed Level shifter is fabricated in a 0.18μm BCD process and occupies an active chip area of 0.034mm2. Simulation results demonstrate that the propagation delay is less than 0.8ns at 50V level shifting and keeps almost constant when the floating ground ranges from -3V to 50V. The positive dV/dt immunity is 300V/ns. The negative dV/dt is 170V/ns under the condition that the level shifting capacitor does not discharge to floating power supply.

A novel ladder control assisted startup for primary side regulated flyback converter without off-chip capacitors is proposed in this paper to reduce the overshoot voltage and optimize the startup time under different loads and input voltages. Large peak current in traditional soft-startup process may damage devices, and the detail reasons are illustrated in this work. To overcome the problems caused by the slow callback process of the error amplifier, sample information relative to the input voltage and load current is used by the ladder control circuit to generate a series of voltages to assist the startup. The proposed controller chip is fabricated in 0.18pm BCD process. The experiment results show that the overshoot voltage can be reduced from 20V to less than 0.3V and startup time can be reduced from 105ms to 42ms with the ladder control.

Type-IV dual-path step-down (T4 DPSD) converter is proposed with conversion efficiency improvement over wide input voltage. The proposed T4 DPSD converter adopts inductor and flying capacitor as power conversion elements, reducing power loss caused by large DCR in conventional Buck converter. Furthermore, the voltage stress of power devices and inductor current ripple are relieved. Thus switching loss and conductance loss are optimized simultaneously. Compared to previously proposed DPSD converters, the proposed T4 DPSD converter features negative voltage switching node. High-swing bootstrap (HSB) gate driver circuit with enhanced PSRR (Power Supply Rejection Ratio) is designed to charge bootstrap capacitor to adequate voltage, even if at lowest input voltage. Consequently, the full load efficiency at 5A is improved from 85% to 89.3%. And the peak conversion efficiency is 95.6% when input voltage is 2.7V to 4.2V with output voltage of 1.2V.

To satisfy fast and high dV/dt immunity driver for wide-bandgap power device applications, speed and dV/dt immunity of the conventional level shifter should be improved. In this paper, a sub-nanosecond level shifter has been proposed, which has ultra-high dV/dt immunity without any additional circuit. Using the edge detection technique, the propagation delay of the proposed level shifter has been reduced significantly. The proposed level shifter is established in a 0.5 μm and a 0.18 μm BCD processes, whose results demonstrate a 520ps propagation delay with the 0.5μm process and a 170ps propagation delay with the 0.18μm process are realized, respectively. More than 250V/ns dV/dt immunity is achieved, which only occupies a 0.022mm2active area with the 0.5μm BCD process.

In high switching frequency applications, for the purpose of the high efficiency and low electromagnetic interference (EMI), an adaptive soft switching technique is proposed in this paper. According to the resonance characteristics of system, a valley point detection circuit is designed. Besides, considering the driving delay of power MOSFET, an adaptive control circuit is proposed to generate a flag signal of driver, by which the adaptive zero voltage switching (AZVS) can be achieved. With the help of proposed AZVS, the precise zero voltage switching independent of driving delay and type of power MOSFET can be automatically realized. An AZVS control circuit is implemented in a 0.35μm BCD process. It allows high efficiency and low EMI, as well as good thermal performance.

This paper presents a new design method based on neural network and co-simulation of MATLAB/Simulink and Virtuoso for solar energy harvesting system to power IoT applications. With the help of this new design method, a solar energy harvesting system with MPPT is designed and fabricated in 0.18 μm CMOS technology. The proposed MPPT scheme was able to track the maximum power point successfully with average tracking errors of 0.30% (pre-simulation) and 0.42% (test). And the efficiency is about 72.9%~76.8% when the light intensity is changing from 5000 lux to 11000 lux. In summary, the proposed new design method has the advantages of high accuracy, controllability and operability.

In this paper, a MOSFET-only voltage reference with novel curvature-compensation is proposed. In order to reduce the temperature coefficient in the proposed voltage reference, two proportional to absolute temperature voltages with opposite second-order order TC are added on a threshold voltage, which is achieved by a resistorless threshold voltage extractor. Besides, self-biased current source with feedback is realized at the same time, which can provide bias current for the whole voltage reference and enhance the performance of generated voltage reference without additional power consumption. Verification results of the proposed voltage reference implemented with 0.35µm technology process show that the temperature coefficient is 2.4 ppm/□ with a temperature range of −20□ to 80□ is obtained, and a 62.9 dB power supply rejection ratio is achieved with a 68nA maximum supply current.

This paper presents a half-select disturb-free 11T static random access memory (SRAM) cell for ultralow-voltage operations. The proposed SRAM cell is well suited for bit-interleaving architecture, which helps to improve the soft-error immunity with error correction coding. The read static noise margin (RSNM) and the write margin (WM) are significantly improved due to its built-in write/read-assist scheme. The experimental results in a 40-nm standard CMOS technology indicate that at a 0.5-V supply voltage, RSNM of the proposed SRAM cell is$19.8\times $and$0.96\times $as that of 6T and 8T SRAM cells with min-area, respectively. It achieves$11.84\times $and$9.56\times $higher WM correspondingly. As a result, a lower minimum operation voltage is obtained. In addition, its leakage power consumption is reduced by 53.3% and 44.5% when compared with 6T and 8T SRAM cell with min-area, respectively.

This paper presents a fully-integrated and fast-transient capacitor-less low-dropout regulator (LDO) with high loop gain and bandwidth in full load range for SoC application. It utilizes a combination of a signal- and transient-current boosting (STCB) error amplifier (EA) with transient enhancement circuit (TEC) and a push-pull differentiator to drive gate capacitance of the power transistor. The STCB-based EA with TEC ensures fast response of the regulator and the differentiator is also adopted to enhance the loop stability while improving transient response simultaneously. Moreover, adaptive biasing is implemented in the circuit to compensate decrease of loop gain and bandwidth at heavy load. The proposed LDO is fabricated in a 0.5μm CMOS process and occupies an active chip area of 0.077mm2. Simulation results demonstrate that it can deliver 100mA load current at 100mV dropout voltage. The voltage spike at the output, undergoing a maximum load current change, is controlled below 300mV and good line/load regulation is achieved at the same time.

In recent years, approximate computing has been widely used in low power digital circuits design. As it incurs error in computation, there are always tradeoffs between hardware performances and computational accuracy. Thus, the circuit implementation can vary from applications to applications and even in the same application, which makes difficult to evaluate the design efficiency in terms of delay, power and computational accuracy. In this paper, approximate efficiency (AE) is proposed as a new design metric dedicated in energy-efficient approximate computation. An automatic pruning approach is presented based on quickly estimated AE, which leads to an efficient approximate circuit design and a significant reduction on energy dissipation. A 32-bit adder is demonstrated using proposed method and compared with other approximation methods, including direct truncation and significance-activity pruning method. For legitimate comparisons, same computational accuracy is obtained for all imprecise adders. The simulation results show that assessed on mean absolute error, the proposed adder outperforms the others. With given error threshold, it can reach 31.15% energy-delay-product reduction compared with the most competitive contender.

Variable on Time (VOT) control is proposed in the paper. Compared to conventional constant on time (COT) control, the on time of VOT control is modulated by output of error amplifier, rather than fixed voltage. VOT controlled buck converter shows significant duty cycle extension than COT control, especially for high switching frequency and wide input/output range applications, such as DVS converters. The duty cycle limitation of COT control is then broken through. The small signal model derivation based on Describing Function (DF) is given. A 1MHz 12V-1.2V buck converter with VOT control is designed with 0.35μm BCD process. Simulation results show that the recovery time is 5μs for 4A load step, and the undershoot voltage is decreased from 50mV to 35mV, by using VOT control. The voltage scaling speed is 20μs/V for 47μF output capacitor. The reference up-tracking shows FOM of 0.42s/(F·V), which is much better than previous works.

Modern low-power system on a chip needs direct current converter with dynamic voltage scaling (DVS) ability for core power supply. The converter output should be accurate voltage across the full load current and voltage scaling range. An integrated buck converter for DVS application is proposed in this brief. Voltage mode phase lead compensation is implemented in the converter, with much smaller passive components than conventional type-III compensation. To improve accuracy, the output voltage error accompanied with load current and reference voltage caused by finite loop gain in analog control loop is corrected by the digital error corrector. The output voltage is compared by two comparators whose threshold voltage is about 10 mV above and below the reference voltage, respectively. The duty cycle is slightly adjusted by finite state machine according to outputs of the two comparators. Experimental results show that the converter is well regulated over an output range of 0.7-1.8 V, with step voltage of 25 mV. When load current suddenly changes between 170 and 500 mA, the overshoot and undershoot voltage are 32 and 50 mV, respectively. Load regulation is maintained about 1% throughout the full load range. The voltage error is within ±10 mV in the voltage scaling range.

A current-efficent, fully integrated low-dropout regulator(LDO) with improved load transient responses for system-on-chips(SoC) is presented in this paper. It makes use of high bandwidth common-gate amplifier and slew-rate enhancement circuit(SRE) triggered by voltage spikes to improve output voltage spike and response time of the LDO greatly. The proposed circuit has been implemented in a 0.35μm standard CMOS process and occupies an active chip area of 0.057mm2. Experimental results show that it can deliver 100mA load current at 150mV dropout voltage. It only consumes 8μA quiescent current and is able to recover within 0.2μs even under the maximum load current change. Consequently, a low-power and ultra-fast capacitor-less LDO can be achieved.

An integrated synchronous buck converter with adaptive dead time controlled driver is presented in this paper. The integrated synchronous buck converter works in 2MHz PWM mode and the output voltage can be programmed by digital interface, which is suitable for powering the processor core and internal memory with dynamic voltage scaling (DVS) capability. The controller provides 0 and 100% duty cycles during DVS, maximizing tracking speed while saving power. The driver circuit detects body diode conduction by a proper biased N-type transistor. The synchronous N-type power MOS is turned on at the falling edge of body diode conduction detection in both DCM and CCM. The P-type power MOS is turned on at the falling edge of dead time detection in CCM. As a result, the dead time varies according to the load current, while the conduction time of the body diode in the synchronous power MOS is approaching to the delay of logic circuit and gate driver. The dead time control logic and gate driver are designed with low time lag to minimize body diode conduction time. Experimental results show that the converter can achieve fast reference tracking and the conversion efficiency is up to 90%.